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MPC5604B/C
MAPBGA-225 15 mm x 15 mm QFN12 ##_mm_x_##mm
MPC5604B/C Microcontroller Data Sheet
32-bit MCU family built on the Power ArchitectureTM for automotive body electronics applications Features: * Single issue, 32-bit CPU core complex (e200z0) -- Compliant with the Power ArchitectureTM embedded category -- Includes an instruction set enhancement allowing variable length encoding (VLE) for code size footprint reduction. With the optional encoding of mixed 16-bit and 32-bit instructions, it is possible to achieve significant code size footprint reduction. Up to 512 Kbytes on-chip flash supported with the flash controller Up to 48 Kbytes on-chip SRAM Memory protection unit (MPU) with 8 region descriptors and 32-byte region granularity Interrupt controller (INTC) with 148 interrupt vectors, including 16 external interrupt sources and 18 external interrupt/wakeup sources Frequency modulated phase-locked loop (FMPLL) Crossbar switch architecture for concurrent access to peripherals, flash, or RAM from multiple bus masters Boot assist module (BAM) supports internal flash programming via a serial link (CAN or SCI) Timer supports input/output channels providing a range of 16-bit input capture, output compare, and pulse width modulation functions (eMIOS-lite) 10-bit analog-to-digital converter (ADC) 3 serial peripheral interface (DSPI) modules Up to 4 serial communication interface (LINFlex) modules
SOT-343R ##_mm_x_##mm
208 MAPBGA (17 x 17 x 1.7 mm)
144 LQFP (20 x 20 x 1.4 mm)
TBD
PKG-TBD ## mm x ## mm
100 LQFP (14 x 14 x 1.4 mm)
* * *
*
* * * *
* * * *
*
Up to 6 enhanced full CAN (FlexCAN) modules with configurable buffers 1 inter IC communication interface (I2C) module Up to 123 configurable general purpose pins supporting input and output operations (package dependent) Real Time Counter (RTC) with clock source from 128 kHz or 16 MHz internal RC oscillator supporting autonomous wakeup with 1 ms resolution with max timeout of 2 seconds Up to 6 periodic interrupt timers (PIT) with 32-bit counter resolution 1 System Module Timer (STM) Nexus development interface (NDI) per IEEE-ISTO 5001-2003 Class Two Plus standard Device/board boundary Scan testing supported with per Joint Test Action Group (JTAG) of IEEE (IEEE 1149.1) On-chip voltage regulator (VREG) for regulation of input supply for all internal levels
* *
* *
* * *
This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. (c) Freescale Semiconductor, Inc., 2009. All rights reserved.
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5604BxMG products in 208 MAPBGA packages
Freescale Semiconductor Data Sheet: Advance Information
Document Number: MPC5604BC Rev. 4, 08/2009
Table of Contents
1 2 General description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Device blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 2.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 2.2 Device block summary . . . . . . . . . . . . . . . . . . . . . . . . . .6 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 4.2 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . .11 4.3 NVUSRO register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.3.1 NVUSRO[PAD3V5V] field description . . . . . . . .11 4.3.2 NVUSRO[OSCILLATOR_MARGIN] field description 12 4.4 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . .12 4.5 Recommended operating conditions . . . . . . . . . . . . . .13 4.6 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . .15 4.6.1 Package thermal characteristics . . . . . . . . . . . .15 4.6.2 Power considerations. . . . . . . . . . . . . . . . . . . . .15 4.7 I/O pad electrical characteristics . . . . . . . . . . . . . . . . . .16 4.7.1 I/O pad types . . . . . . . . . . . . . . . . . . . . . . . . . . .16 4.7.2 I/O input DC characteristics . . . . . . . . . . . . . . . .17 4.7.3 I/O output DC characteristics. . . . . . . . . . . . . . .17 4.7.4 Output pin transition times . . . . . . . . . . . . . . . . .20 4.7.5 I/O pad current specification . . . . . . . . . . . . . . .21 4.8 nRSTIN electrical characteristics . . . . . . . . . . . . . . . . .23 4.9 Power management electrical characteristics. . . . . . . .25 4.9.1 Voltage regulator electrical characteristics . . . .25 4.9.2 Voltage monitor electrical characteristics. . . . . .27 4.10 Low voltage domain power consumption . . . . . . . . . . .28 4.11 Flash memory electrical characteristics . . . . . . . . . . . .29 4.11.1 Program/Erase characteristics . . . . . . . . . . . . . 29 4.11.2 Flash power supply DC characteristics . . . . . . 31 4.11.3 Start-up/Switch-off timings . . . . . . . . . . . . . . . . 31 4.12 Electromagnetic compatibility (EMC) characteristics. . 32 4.12.1 Designing hardened software to avoid noise problems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.12.2 Electromagnetic interference (EMI) . . . . . . . . . 32 4.12.3 Absolute maximum ratings (electrical sensitivity)33 4.13 Fast external crystal oscillator (4 to 16 MHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.14 Slow external crystal oscillator (32 kHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.15 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . 39 4.16 Fast internal RC oscillator (16 MHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.17 Slow internal RC oscillator (128 kHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.18 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.18.1 Current consumption . . . . . . . . . . . . . . . . . . . . 42 4.18.2 DSPI characteristics. . . . . . . . . . . . . . . . . . . . . 44 4.18.3 Nexus characteristics . . . . . . . . . . . . . . . . . . . . 50 4.18.4 JTAG characteristics. . . . . . . . . . . . . . . . . . . . . 51 4.18.5 ADC electrical characteristics . . . . . . . . . . . . . 52 5 Package characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 5.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . 60 6 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 7 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Appendix A Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
3 4
MPC5604B/C Microcontroller Data Sheet, Rev. 4 2 Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5604BxMG products in 208 MAPBGA packages
General description
1
1.1
General description
Introduction
The MPC5604B/C is a family of next generation microcontrollers built on the Power ArchitectureTM embedded category. This document describes the features of the family and options available within the family members, and highlights important electrical and physical characteristics of the device1. The MPC5604B/C family of 32-bit microcontrollers is the latest achievement in integrated automotive application controllers. It belongs to an expanding family of automotive-focused products designed to address the next wave of body electronics applications within the vehicle. The advanced and cost-efficient host processor core of the MPC5604B/C automotive controller family complies with the Power Architecture embedded category and only implements the VLE (variable-length encoding) APU, providing improved code density. It operates at speeds of up to 64 MHz and offers high performance processing optimized for low power consumption. It capitalizes on the available development infrastructure of current Power Architecture devices and is supported with software drivers, operating systems and configuration code to assist with users implementations. Table 1. MPC5604B/C device comparison1
Device Feature MPC560 MPC560 MPC560 MPC560 MPC560 MPC560 MPC560 MPC560 MPC560 MPC560 2BxLL 2BxLQ 2CxLL 3BxLL 3BxLQ 3CxLL 4BxLL 4BxLQ 4BxMG 4CxLL e200z0h Static - 64 MHz 256 KB 384 KB 64 KB (4 x 16 KB) 24 KB 32 KB 28 KB 40 KB 8-entry 28 ch, 10-bit 36 ch, 10-bit 28 ch, 10-bit 36 ch, 10-bit Yes 28 ch, 16-bit 5 ch 20 ch 3 ch 3 56 ch, 16-bit 10 ch 40 ch 6 ch 28 ch, 16-bit 56ch, 16-bit 10 ch 40 ch 6 ch 4 3 2 6 3 6 3 3 6 6 28 ch, 16-bit 56 ch, 16-bit 28 ch, 16-bit 5 ch 20 ch 3 ch 4 28 ch, 10-bit 28 ch, 10-bit 36 ch, 10-bit 36 ch, 10-bit 28 ch, 10-bit 32 KB 48 KB 512 KB
CPU Execution speed2 Code Flash Data Flash RAM MPU ADC CTU Total timer I/O3 eMIOS * PWM + MC + IC/OC4 * PWM + IC/OC4 * IC/OC4 SCI (LINFlex) SPI (DSPI) CAN (FlexCAN)
5 ch 20 ch 3 ch 4
5 ch 20 ch 3 ch
5 ch 20 ch 3 ch 4
5 ch 20 ch 3 ch
10 ch 40 ch 6 ch 4
10 ch 40 ch 6 ch
1.For a correct use of the datasheet, it's recommended of referring to the errata sheet.
MPC5604B/C Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 3
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5604BxMG products in 208 MAPBGA packages
General description
Table 1. MPC5604B/C device comparison1 (continued)
Device Feature MPC560 MPC560 MPC560 MPC560 MPC560 MPC560 MPC560 MPC560 MPC560 MPC560 2BxLL 2BxLQ 2CxLL 3BxLL 3BxLQ 3CxLL 4BxLL 4BxLQ 4BxMG 4CxLL 1 Yes 79 123 79 79 JTAG 100 LQFP 144 LQFP 100 LQFP 100 LQFP 144 LQFP 100 LQFP 100 LQFP 144 LQFP 123 79 79 123 123 Nexus2+ 208 MA PBGA6 79 JTAG 100 LQFP
I2C 32 kHz oscillator GPIO5 Debug Package
1 2 3 4 5 6
Feature set dependent on selected peripheral multiplexing--table shows example implementation Based on 105 C ambient operating temperature Refer to eMIOS section of device reference manual for information on the channel configuration and functions IC - Input Capture; OC - Output Compare; PWM - Pulse Width Modulation; MC - Modulus counter I/O count based on multiplexing with peripherals 208 MAPBGA available only as development package for Nexus2+
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4 4 Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5604BxMG products in 208 MAPBGA packages
Device blocks
2
2.1
Device blocks
Block diagram
Figure 1. MPC5604B/C series block diagram
TCU JTAG Port Nexus Port Nexus NMI SIUL Voltage Regulator NMI Interrupt requests from peripheral blocks INTC Clocks FMPLL CMU Instructions e200z0h (Master) Data Nexus 2+ (Master) 64-bit 2 x 3 Crossbar Switch JTAG RAM 48 KB Code Flash DataFlash 512 KB 64 KB
Figure 1 shows a top-level block diagram of the MPC5604B/C device series.
SRAM Controller MPU
Flash Controller
(Slave) (Slave) (Slave)
MPU Registers
RTC
STM
SWT
ECSM
PIT
RGM
CGM
MEM
PCU
BAM
SSCM
Peripheral Bridge
Interrupt Request
SIUL Reset Control External Interrupt Request IMUX GPIO & Pad Control
36 Ch. ADC
CTU
2x eMIOS
4x LINFlex
3x DSPI
I2C
6x FlexCAN
I/O Legend: ADC BAM CAN CGM CMU CTU DSPI eMIOS FMPLL I2C IMUX INTC JTAG LINFlex
...
...
...
...
...
Analog-to-Digital Converter Boot Assist Module Controller Area Network (FlexCAN) Clock Generation Module Clock Monitor Unit Cross Triggering Unit Deserial Serial Peripheral Interface Enhanced Modular Input Output System Frequency-Modulated Phase-Locked Loop Inter-integrated Circuit Bus Internal Multiplexer Interrupt Controller JTAG controller Serial Communication Interface (LIN support)
MEM MPU Nexus NMI PCU PIT RGM RTC SIUL SRAM SSCM STM SWT TCU
Mode Entry Module Memory Protection Unit NexuS Development Interface (NDI) Level Non-Maskable Interrupt Power Control Unit Periodic Interrupt Timer Reset Generation Module Real-Time Clock System Integration Unit Lite Static Random-Access Memory System Status Configuration Module System Timer Module Software Watchdog Timer Test Control Unit
MPC5604B/C Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 5
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5604BxMG products in 208 MAPBGA packages
Device blocks
2.2
Device block summary
Table 2. MPC5604B/C series block summary
Block Crossbar (XBAR) switch Function Supports simultaneous connections between two master ports and three slave ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus width
Table 2 summarizes the functions of all blocks present in the MPC5604B/C series of microcontrollers. Please note that the presence and number of blocks varies by device and package.
Analog-to-digital converter (ADC) Multi-channel, 10-bit analog-to digital-converter Boot assist module (BAM) Clock generation module (CGM) Clock monitor unit (CMU) Cross triggering unit (CTU) A block of read-only memory containing VLE code which is executed according to the boot mode of the device Provides logic and control required for the generation of system and peripheral clocks Monitors clock source (internal and external) integrity Enables synchronization of ADC conversions with a timer event from the eMIOS or from the PIT
Deserial serial peripheral interface Provides a synchronous serial interface for communication with external devices (DSPI) Enhanced modular input output system (eMIOS) Flash memory Provides the functionality to generate or measure events Provides non-volatile storage for program code, constants and variables
FlexCAN (controller area network) Supports the standard CAN communications protocol FMPLL (frequency-modulated phase-locked loop) Internal multiplexer (IMUX) SIU subblock Generates high-speed system clocks and supports programmable frequency modulation Allows flexible mapping of peripheral interface on the different pins of the device
Inter-integrated circuit (I2CTM) bus A two wire bidirectional serial bus that provides a simple and efficient method of data exchange between devices Interrupt controller (INTC) JTAG controller LINflex controller Memory protection unit (MPU) Mode entry module (MC_ME) Provides priority-based preemptive scheduling of interrupt requests Provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode Manages a high number of LIN (Local Interconnect Network protocol) messages efficiently with a minimum of CPU load Provides hardware access control for all memory references generated in a device Provides a mechanism for controlling the device operational mode and mode transition sequences in all functional states; also manages the power control unit, reset generation module and clock generation module, and holds the configuration, control and status registers accessible for applications Handles external events that must produce an immediate response, such as power down detection Provides real-time development support capabilities in compliance with the IEEE-ISTO 5001-2003 standard
Non-Maskable Interrupt (NMI) Nexus development interface (NDI)
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4 6 Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5604BxMG products in 208 MAPBGA packages
Device blocks
Table 2. MPC5604B/C series block summary (continued)
Block Periodic interrupt timer (PIT) Power control unit (PCU) Function Produces periodic interrupts and triggers Reduces the overall power consumption by disconnecting parts of the device from the power supply via a power switching device; device components are grouped into sections called "power domains" which are controlled by the PCU A free running counter used for time keeping applications, the RTC can be configured to generate an interrupt at a predefined interval independent of the mode of operation (run mode or low-power mode) Centralizes reset sources and manages the device reset sequence of the device Provides storage for program code, constants, and variables Provides control over all the electrical pad controls and up 32 ports with 16 bits of bidirectional, general-purpose input and output signals and supports up to 32 external interrupts with trigger event configuration Provides system configuration and status data (such as memory size and status, device mode and security status), device identification data, debug status port enable and selection, and bus and peripheral abort enable/disable Provides a set of output compare events to support AUTOSAR and operating system tasks Provides protection from runaway code An extension of the JTAG controller module, the TCU provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode.
Real-time counter (RTC)
Reset generation module (RGM) Static random-access memory (SRAM) System integration unit (SIU)
System status configuration module (SSCM) System timer module (STM) System watchdog timer (SWT) Test control unit (TCU)
MPC5604B/C Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 7
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5604BxMG products in 208 MAPBGA packages
Package pinouts
3
Package pinouts
Figure 2. LQFP 144-pin configuration (top view)
PB[2] / GPIO[18] / LIN0TX / SDA PC[8] / GPIO[40] / LIN2TX PC[13] / GPIO[45] / E0UC[13] / SOUT_2 PC[12] / GPIO[44] / E0UC[12] / SIN_2 PE[7] / GPIO[71] / E0UC[23] / CS2_0 / MA[0] PE[6] / GPIO[70] / E0UC[22] / CS3_0 / MA[1] PH[8] / GPIO[120] / E1UC[10] / CS2_2 / MA[0] PH[7] / GPIO[119] / E1UC[9] / CS3_2 / MA[1] PH[6] / GPIO[118] / E1UC[8] MA[2] PH[5] / GPIO[117] / E1UC[7] PH[4] / GPIO[116] / E1UC[6] PE[5] / GPIO[69] / E0UC[21] / CS0_1 / MA[2] PE[4] / GPIO[68] / E0UC[20] / SCK_1 / EIRQ[9] PC[4] / GPIO[36] / SIN_1 / CAN3RX PC[5] / GPIO[37] / SOUT_1 / CAN3TX / EIRQ[7] PE[3] / GPIO[67] / E0UC[19] / SOUT_1 PE[2] / GPIO[66] / E0UC[18] / SIN_1 PH[9] / GPIO[121] / TCK PC[0] / GPIO[32] / TDI VSS_LV VDD_LV VDD_HV VSS_HV PC[1] / GPIO[33] / TDO PH[10] / GPIO[122] / TMS PA[6] / GPIO[6] / E0UC[6] / EIRQ[1] PA[5] / GPIO[5] / E0UC[5] PC[2] / GPIO[34] / SCK_1 / CAN4TX / EIRQ[5] PC[3] / GPIO[35] / CS0_1 / MA[0] / CAN1RX / CAN4RX / EIRQ[6] PG[11] / GPIO[107] / E0UC[25] PG[10] / GPIO[106] / E0UC[24] PE[15] / GPIO[79] / CS0_2 / E1UC[22] PE[14] / GPIO[78] / SCK_2 / E1UC[21] / EIRQ[12] PG[15] / GPIO[111] / E1UC[1] PG[14] / GPIO[110] / E1UC[0] PE[12] / GPIO[76] / SIN_2 / E1UC[19] / EIRQ[11]
The available LQFP pinouts and the 208 MAPBGA ballmap are provided in the following figures. For pin signal descriptions, please refer to the device reference manual.
WKUP[11] / SCL / LIN0RX / GPIO[19] / PB[3] WKUP[13] / LIN2RX / GPIO[41] / PC[9] EIRQ[8] / SCK2 / E0UC[14] / GPIO[46] / PC[14] CS0_2 / E0UC[15] / GPIO[47] / PC[15] WKUP[18] / E1UC[14] / GPIO[101] / PG[5] E1UC[13] / GPIO[100] / PG[4] WKUP[17] / E1UC[12] / GPIO[99] / PG[3] E1UC[11] / GPIO[98] / PG[2] WKUP[3] / E0UC[2] / GPIO[2] / PA[2] WKUP[6] / CAN5RX / E0UC[16] / GPIO[64] / PE[0] WKUP[2] / NMI / E0UC[1] / GPIO[1] / PA[1] CAN5TX / E0UC[17] / GPIO[65] / PE[1] CAN3TX / E0UC[22] / CAN2TX / GPIO[72] / PE[8] WKUP[7] / E0UC[23] / CAN3RX / CAN2RX / GPIO[73] / PE[9] EIRQ[10] / CS3_1 / LIN3TX / GPIO[74] / PE[10] WKUP[19] / CLKOUT / E0UC[0] / GPIO[0] / PA[0] WKUP[14] / CS4_1 / LIN3RX / GPIO[75] / PE[11] VSS_HV VDD_HV VSS_HV RESET VSS_LV VDD_LV VDD_BV SCK_2 / E1UC[18] / GPIO[105] / PG[9] EIRQ[15] / CS0_2 / E1UC[17] / GPIO[104] / PG[8] WKUP[5] / CAN4RX / CAN1RX / GPIO[43] / PC[11] MA[1] / CAN4TX / CAN1TX / GPIO[42] / PC[10] E1UC[16] / GPIO[103] / PG[7] E1UC[15] / GPIO[102] / PG[6] CAN0TX / GPIO[16] / PB[0] WKUP[4] / CAN0RX / GPIO[17] / PB[1] CS5_0 / CAN3RX / CAN2RX / GPIO[89] / PF[9] CS4_0 / CAN3TX / CAN2TX / GPIO[88] / PF[8] E1UC[25] / GPIO[92] / PF[12] LIN1TX / GPIO[38] / PC[6]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
144 LQFP
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
PA[11] / GPIO[11] / E0UC[11] / SCL PA[10] / GPIO[10] / E0UC[10] / SDA PA[9] / GPIO[9] / E0UC[9] / FAB PA[8] / GPIO[8] / E0UC[8] / LIN3RX / EIRQ[3] / ABS[0] PA[7] / GPIO[7] / E0UC[7] / LIN3TX / EIRQ[2] PE[13] / GPIO[77] / SOUT2 / E1UC[20] PF[14] / GPIO[94] / CAN1TX / CAN4TX / E1UC[27] PF[15] / GPIO[95] / CAN1RX / CAN4RX / EIRQ[13] VDD_HV VSS_HV PG[0] / GPIO[96] / CAN5TX / E1UC[23] PG[1] / GPIO[97] / CAN5RX / E1UC[24] / EIRQ[14] PH[3] / GPIO[115] / E1UC[5] / CS0_1 PH[2] / GPIO[114] / E1UC[4] / SCK1 PH[1] / GPIO[113] / E1UC[3] / SOUT1 PH[0] / GPIO[112] / E1UC[2] / SIN1 PG[12] / GPIO[108] / E0UC[26] PG[13] / GPIO[109] / E0UC[27] PA[3] / GPIO[3] / E0UC[3] / EIRQ[0] PB[15] / GPIO[31] / CS4_0 / E0UC[7] / ANX[3] PD[15] / GPIO[63] / CS2_1 / ANS[7] / E0UC[27] PB[14] / GPIO[30] / CS3_0 / E0UC[6] / ANX[2] PD[14] / GPIO[62] / CS1_1 / ANS[6] / E0UC[26] PB[13] / GPIO[29] / CS2_0 / E0UC[5] / ANX[1] PD[13] / GPIO[61] / CS0_1 / ANS[5] / E0UC[25] PB[12] / GPIO[28] / CS1_0 / E0UC[4] / ANX[0] PD[12] / GPIO[60] / CS5_0 / ANS[4] / E0UC[24] PB[11] / GPIO[27] / E0UC[3] / ANS[3] / CS0_0 PD[11] / GPIO[59] / ANP[15] PD[10] / GPIO[58] / ANP[14] PD[9] / GPIO[57] / ANP[13] PB[7] / GPIO[23] / ANP[3] PB[6] / GPIO[22] / ANP[2] PB[5] / GPIO[21] / ANP[1] VDD_HV_ADC VSS_HV_ADC
Note: Availability of port pin alternate functions depends on product selection.
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4 8 Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5604BxMG products in 208 MAPBGA packages
WKUP[12] / LIN1RX / GPIO[39] / PC[7] GPIO[90] / PF[10] WKUP[15] / GPIO[91] / PF[11] WKUP[10] / SCK_0 / CS0_0 / GPIO[15] / PA[15] WKUP[16] / E1UC[26] / GPIO[93] / PF[13] EIRQ[4] / CS0_0 / SCK_0 / GPIO[14] / PA[14] WKUP[9] / E0UC[4] / GPIO[4] / PA[4] SOUT_0 / GPIO[13] / PA[13] SIN_0 / GPIO[12] / PA[12] VDD_LV VSS_LV XTAL VSS_HV EXTAL VDD_HV OSC32K_EXTAL / ANS[1] / GPIO[25] / PB[9] OSC32K_XTAL / ANS[0] / GPIO[24] / PB[8] WKUP[8] / ANS[2] / GPIO[26] / PB[10] CS3_1 / ANS[8] / E0UC[10] / GPIO[80] / PF[0] CS4_1 / ANS[9] / E0UC[11] / GPIO[81] / PF[1] CS0_2 / ANS[10] / E0UC[12] / GPIO[82] / PF[2] CS1_2 / AN1[11] / E0UC[13] / GPIO[83] / PF[3] CS2_2 / ANS[12] / E0UC[14] / GPIO[84] / PF[4] CS3_2 / ANS[13] / E0UC[22] / GPIO[85] / PF[5] ANS[14] / E0UC[23] / GPIO[86] / PF[6] ANS[15] / GPIO[87] / PF[7] ANP[4] / GPIO[48] / PD[0] ANP[5] / GPIO[49] / PD[1] ANP[6] / GPIO[50] / PD[2] ANP[7] / GPIO[51] / PD[3] ANP[8] / GPIO[52] / PD[4] ANP[9] / GPIO[53] / PD[5] ANP[10] / GPIO[54] / PD[6] ANP[11] / GPIO[55] / PD[7] ANP[12] / GPIO[56] / PD[8] ANP[0] / GPIO[20] / PB[4]
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
Package pinouts
Figure 3. LQFP 100-pin configuration (top view)
WKUP[11] / SCL / LIN0RX / GPIO[19] / PB[3] WKUP[13] / LIN2RX / GPIO[41] / PC[9] EIRQ[8] / SCK2 / E0UC[14] / GPIO[46] / PC[14] CS0_2 / E0UC[15] / GPIO[47] / PC[15] WKUP[3] / E0UC[2] / GPIO[2] / PA[2] WKUP[6] / CAN5RX / E0UC[16] / GPIO[64] / PE[0] WKUP[2] / NMI / E0UC[1] / GPIO[1] / PA[1] CAN5TX / E0UC[17] / GPIO[65] / PE[1] CAN3TX / E0UC[22] /CAN2TX / GPIO[72] / PE[8] WKUP[7] / CAN3RX / E0UC[23] /CAN2RX / GPIO[73] / PE[9] EIRQ[10] / CS3_1 / LIN3TX / GPIO[74] / PE[10] WKUP[19] / CLKOUT / E0UC[0] / GPIO[0] / PA[0] WKUP[14] / CS4_1 / LIN3RX / GPIO[75] / PE[11] VSS_HV VDD_HV VSS_HV RESET VSS_LV VDD_LV VDD_BV WKUP[5] / CAN4RX / CAN1RX / GPIO[43] / PC[11] MA[1] / CAN4TX / CAN1TX / GPIO[42] / PC[10] CAN0TX / GPIO[16] / PB[0] WKUP[4] / CAN0RX / GPIO[17] / PB[1] LIN1TX / GPIO[38] / PC[6]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
100 LQFP
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
PA[11] / GPIO[11] / E0UC[11] / SCL PA[10] / GPIO[10] / E0UC[10] / SDA PA[9] / GPIO[9] / E0UC[9] / FAB PA[8] / GPIO[8] / E0UC[8] / LIN3RX / EIRQ[3] / ABS[0] PA[7] / GPIO[7] / E0UC[7] / LIN3TX / EIRQ [2] VDD_HV VSS_HV PA[3] / GPIO[3] / E0UC[3] / EIRQ[0] PB[15] / GPIO[31] / CS4_0 / E0UC[7] / ANX[3] PD[15] / GPIO[63] / CS2_1 / ANS[7] / E0UC[27] PB[14] / GPIO[30] / CS3_ 0 / E0UC[6] / ANX[2] PD[14] / GPIO[62] / CS1_1 / ANS[6] / E0UC[26] PB[13] / GPIO[29] / CS2_0 / E0UC[5] / ANX[1] PD[13] / GPIO[61] / CS0_1 / ANS[5] / E0UC[25] PB[12] / GPIO[28] / CS1_0 / E0UC[4] / ANX[0] PD[12] / GPIO[60] / CS5_0 / ANS[4] / E0UC[24] PB[11] / GPIO[27] / E0UC[3] / ANS[3] / CS0_0 PD[11] / GPIO[59] / ANP[15] PD[10] / GPIO[58] / ANP[14] PD[9] / GPIO[57] / ANP[13] PB[7] / GPIO[23] / ANP[3] PB[6] / GPIO[22] / ANP[2] PB[5] / GPIO[21] / ANP[1] VDD_HV_ADC VSS_HV_ADC
Note: Availability of port pin alternate functions depends on product selection.
MPC5604B/C Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 9
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5604BxMG products in 208 MAPBGA packages
WKUP[12] / LIN1RX / GPIO[39] / PC[7] WKUP[10] / SCK0 / CS0_0 / GPIO[15] / PA[15] EIRQ[4] / CS0_0 / SCK0 / GPIO[14] / PA[14] WKUP[9] / E0UC[4] / GPIO[4] / PA[4] SOUT_0 / GPIO[13] / PA[13] SIN_0 / GPIO[12] / PA[12] VDD_LV VSS_LV XTAL VSS_HV EXTAL VDD_HV OSC32K_EXTAL / ANS[1] / GPIO[25] / PB[9] OSC32K_XTAL / ANS[0] / GPIO[24] / PB[8] WKUP[8] / ANS[2] / GPIO[26] / PB[10] ANP[4] / GPIO[48] / PD[0] ANP[5] / GPIO[49] / PD[1] ANP[6] / GPIO[50] / PD[2] ANP[7] / GPIO[51] / PD[3] ANP[8] / GPIO[52] / PD[4] ANP[9] / GPIO[53] / PD[5] ANP[10] / GPIO[54] / PD[6] ANP[11] / GPIO[55] / PD[7] ANP[12] / GPIO[56] / PD[8] ANP[0] / GPIO[20] / PB[4]
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
PB[2] / GPIO[18] / LIN0TX / SDA PC[8] / GPIO[40] / LIN2TX PC[13] / GPIO[45] / E0UC[13] / SOUT_2 PC[12] / GPIO[44] / E0UC[12] / SIN_2 PE[7] / GPIO[71] / E0UC[23] / CS2_0 / MA[0] PE[6] / GPIO[70] / E0UC[22] / CS3_0 / MA[1] PE[5] / GPIO[69] / E0UC[21] / CS0_1 / MA[2] PE[4] / GPIO[68] / E0UC[20] / SCK_1 / EIRQ[9] PC[4] / GPIO[36] / SIN1 / CAN3RX PC[5] / GPIO[37] / SOUT_1 / CAN3TX / EIRQ[7] PE[3] / GPIO[67] / E0UC[19] / SOUT_1 PE[2] / GPIO[66] / E0UC[18] / SIN_1 PH[9] / GPIO[121] / TCK PC[0] / GPIO[32] / TDI VSS_LV VDD_LV VDD_HV VSS_HV PC[1] / GPIO[33] / TDO PH[10] / GPIO[122] / TMS PA[6] / GPIO[6] / E0UC[6] / EIRQ[1] PA[5] / GPIO[5] / E0UC[5] PC[2] / GPIO[34] / SCK1 / CAN4TX / EIRQ[5] PC[3] / GPIO[35] / CS0_1 / MA[0] / CAN1RX / CAN4RX / EIRQ[6] PE[12] / GPIO[76] / SIN_2 / EIRQ[11]
Electrical characteristics Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5604BxMG products in 208 MAPBGA packages
1 A B C D E F G H J K L M N P R T
PC[8]
2
PC[13]
3
NC
4
NC
5
PH[8]
6
PH[4]
7
PC[5]
8
PC[0]
9
NC
10
NC
11
PC[2]
12
NC
13
PE[15]
14
NC
15
NC
16
NC
A B C D E F G H J K L M N P R T
PC[9]
PB[2]
NC
PC[12]
PE[6]
PH[5]
PC[4]
PH[9]
PH[10]
NC
PC[3]
PG[11]
PG[15]
PG[14]
PA[11]
PA[10]
PC[14]
VDD_HV
PB[3]
PE[7]
PH[7]
PE[5]
PE[3]
VSS_LV
PC[1]
NC
PA[5]
NC
PE[14]
PE[12]
PA[9]
PA[8]
NC
NC
PC[15]
NC
PH[6]
PE[4]
PE[2]
VDD_LV
VDD_HV
NC
PA[6]
NC
PG[10]
PF[14]
PE[13]
PA[7]
PG[4]
PG[5]
PG[3]
PG[2]
PG[1]
PG[0]
PF[15]
VDD_HV
PE[0]
PA[2]
PA[1]
PE[1]
PH[0]
PH[1]
PH[3]
PH[2]
PE[9]
PE[8]
PE[10]
PA[0]
VSS_HV VSS_HV VSS_HV VSS_HV
VDD_HV
NC
NC
MSEO
VSS_HV
PE[11]
VDD_HV
NC
VSS_HV VSS_HV VSS_HV VSS_HV
MDO3
MDO2
MDO0
MDO1
RESET
VSS_LV
NC
NC
VSS_HV VSS_HV VSS_HV VSS_HV
NC
NC
NC
NC
EVTI
NC
VDD_BV
VDD_LV
VSS_HV VSS_HV VSS_HV VSS_HV
NC
PG[12]
PA[3]
PG[13]
PG[9]
PG[8]
NC
EVTO
PB[15]
PD[15]
PD[14]
PB[14]
PG[7]
PG[6]
PC[10]
PC[11]
PB[13]
PD[13]
PD[12]
PB[12]
PB[1]
PF[9]
PB[0]
NC
NC
PA[4]
VSS_LV
EXTAL
VDD_HV
PF[0]
PF[4]
NC
PB[11]
PD[10] VDD_HV _ADC PD[7]
PD[9]
PD[11]
PF[8]
NC
PC[7]
NC
NC
PA[14]
VDD_LV
XTAL
PB[10] OSC32K _XTAL OSC32K _EXTAL
PF[1]
PF[5]
PD[0]
PD[3]
PB[6] VSS_HV _ADC PD[8]
PB[7]
PF[12]
PC[6]
PF[10]
PF[11]
VDD_HV
PA[15]
PA[13]
NC
PF[3]
PF[7]
PD[2]
PD[4]
PB[5]
NC
NC
NC
MCKO
NC
PF[13]
PA[12]
NC
PF[2]
PF[6]
PD[1]
PD[5]
PD[6]
PB[4]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
NC
15
16
Note: 208 MAPBGA available only as development package for Nexus 2+.
= Not connected
Figure 4. 208 MAPBGA configuration
4
4.1
Electrical characteristics
Introduction
This section contains electrical characteristics of the device as well as temperature and power considerations. This product contains devices to protect the inputs against damage due to high static voltages. However, it is advisable to take precautions to avoid application of any voltage higher than the specified maximum rated voltages. To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (VDD or VSS). This could be done by the internal pull-up and pull-down, which is provided by the product for most general purpose pins. The parameters listed in the following tables represent the characteristics of the device and its demands on the system.
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4 10 Freescale Semiconductor
Electrical characteristics
In the tables where the device logic provides signals with their respective timing characteristics, the symbol "CC" for Controller Characteristics is included in the Symbol column. In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol "SR" for System Requirement is included in the Symbol column.
CAUTION
All of the following figures are indicative and must be confirmed during either silicon validation, silicon characterization or silicon reliability trial.
4.2
Parameter classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding, the classifications listed in Table 3 are used and the parameters are tagged accordingly in the tables where appropriate. Table 3. Parameter classifications
Classification tag P C T Tag description Those parameters are guaranteed during production testing on each individual device. Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. Those parameters are derived mainly from simulations.
D
NOTE
The classification is shown in the column labeled "C" in the parameter tables where appropriate.
4.3
NVUSRO register
Portions of the device configuration, such as high voltage supply, oscillator margin, and watchdog enable/disable after reset are controlled via bit values in the Non-Volatile User Options Register (NVUSRO) register.
4.3.1
NVUSRO[PAD3V5V] field description
Table 4. PAD3V5V field description1
Value2 0 1
1 2
Table 4 shows how NVUSRO[PAD3V5V] controls the device configuration.
Description High voltage supply is 5.0 V High voltage supply is 3.3 V
See the device reference manual for more information on the NVUSRO register. '1' is delivery value. It is part of shadow Flash, thus programmable by customer.
The DC electrical characteristics are dependent on the PAD3V5V bit value.
MPC5604B/C Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 11
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5604BxMG products in 208 MAPBGA packages
Electrical characteristics
4.3.2
NVUSRO[OSCILLATOR_MARGIN] field description
Table 5. OSCILLATOR_MARGIN field description1
Value2 0 1
1 2
Table 5 shows how NVUSRO[OSCILLATOR_MARGIN] controls the device configuration.
Description Low consumption configuration (4 MHz/8 MHz) High margin configuration (4 MHz/16 MHz)
See the device reference manual for more information on the NVUSRO register. '1' is delivery value. It is part of shadow Flash, thus programmable by customer.
The fast external crystal oscillator consumption is dependent on the OSCILLATOR_MARGIN bit value.
4.4
Absolute maximum ratings
Table 6. Absolute maximum ratings
Value Symbol VSS VDD VSS_LV Parameter Conditions Min SR Digital ground on VSS_HV pins SR Voltage on VDD_HV pins with respect to ground (VSS) SR Voltage on VSS_LV (low voltage digital supply) pins with respect to ground (VSS) SR Voltage on VDD_BV pin (regulator supply) with respect to ground (VSS) -- -- -- 0 -0.3 Max 0 6.0 V V V Unit
VSS-0.1 VSS+0.1
VDD_BV
-- Relative to VDD --
-0.3 -0.3
5.5 VDD+0.3
V
VSS_ADC SR Voltage on VSS_HV_ADC (ADC reference) pin with respect to ground (VSS) VDD_ADC SR Voltage on VDD_HV_ADC pin (ADC reference) with respect to ground (VSS) VIN SR Voltage on any GPIO pin with respect to ground (VSS) SR Injected input current on any pin during overload condition SR Absolute sum of all injected input currents during overload condition
VSS-0.1 VSS+0.1
V
-- Relative to VDD -- Relative to VDD -- --
-0.3
5.5
V
VDD -0.3 VDD+0.3 -0.3 5.5 V VDD -0.3 VDD+0.3 -10 -50 -- -- -- -55 10 50 70 64 150 150 mA C mA mA
IINJPAD IINJSUM
IAVGSEG SR Sum of all the static I/O current within a VDD = 5.0 V 10%, PAD3V5V = 0 supply segment VDD = 3.3 V 10%, PAD3V5V = 1 ICORELV SR Low voltage static current sink through VDD_BV TSTORAGE SR Storage temperature -- --
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4 12 Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5604BxMG products in 208 MAPBGA packages
Electrical characteristics
NOTE
Stresses exceeding the recommended absolute maximum ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification are not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions (VIN > VDD or VIN < VSS), the voltage on pins with respect to ground (VSS) must not exceed the recommended values.
4.5
Recommended operating conditions
Table 7. Recommended operating conditions (3.3 V)
Value Symbol VSS VDD1 VSS_LV2 Parameter SR Digital ground on VSS_HV pins SR Voltage on VDD_HV pins with respect to ground (VSS) SR Voltage on VSS_LV (low voltage digital supply) pins with respect to ground (VSS) SR Voltage on VDD_BV pin (regulator supply) with respect to ground (VSS) SR Voltage on VSS_HV_ADC (ADC reference) pin with respect to ground (VSS) SR Voltage on VDD_HV_ADC pin (ADC reference) with respect to ground (VSS) SR Voltage on any GPIO pin with respect to ground (VSS) SR Injected input current on any pin during overload condition SR Absolute sum of all injected input currents during overload condition SR VDD slope to ensure correct power up6 Conditions Min -- -- -- 0 3.0 Max 0 3.6 V V V Unit
VSS-0.1 VSS+0.1
VDD_BV3
-- Relative to VDD --
3.0
3.6
V
VDD-0.1 VDD+0.1 VSS-0.1 VSS+0.1 V
VSS_ADC
VDD_ADC4
-- Relative to VDD -- Relative to VDD -- -- -- --
3.05
3.6
V
VDD-0.1 VDD+0.1 VSS-0.1 -- -5 -50 -- 3 -40 -- VDD+0.1 5 50 0.25 -- 125 150 V/s V/s C mA V
VIN
IINJPAD IINJSUM TVDD
TA TJ
1 2
SR Ambient temperature under bias SR Junction temperature under bias
fCPU < 64 MHz --
-40
100 nF capacitance needs to be provided between each VDD/VSS pair 330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair. 3 100 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed depending on external regulator characteristics). 4 100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair.
MPC5604B/C Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 13
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5604BxMG products in 208 MAPBGA packages
Electrical characteristics
5
Full electrical specification cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical characteristics and I/Os DC electrical specification may not be guaranteed. When voltage drops below VLVDHVL, device is reset. 6 Guaranteed by device validation
Table 8. Recommended operating conditions (5.0 V)
Value Symbol VSS VDD1 VSS_LV3 Parameter SR Digital ground on VSS_HV pins SR Voltage on VDD_HV pins with respect to ground (VSS) SR Voltage on VSS_LV (low voltage digital supply) pins with respect to ground (VSS) SR Voltage on VDD_BV pin (regulator supply) with respect to ground (VSS) Conditions Min -- -- Voltage drop2 -- 0 4.5 3.0 Max 0 5.5 5.5 V V V Unit
VSS-0.1 VSS+0.1
VDD_BV4
-- Voltage drop(2)
4.5 3.0
5.5 5.5
V
Relative to VDD VSS_ADC SR Voltage on VSS_HV_ADC (ADC reference) pin with respect to ground (VSS SR Voltage on VDD_HV_ADC pin (ADC reference) with respect to ground (VSS) --
VDD-0.1 VDD+0.1 VSS-0.1 VSS+0.1 V
VDD_ADC5
-- Voltage drop(2) Relative to VDD
4.5 3.0
5.5 5.5
V
VDD-0.1 VDD+0.1 VSS-0.1 -- -5 -50 -- 3 -40 -40 -40 -40 -40 -40 -- VDD+0.1 5 50 0.25 -- 85 110 105 130 125 150 V/s V/s C mA V
VIN
SR Voltage on any GPIO pin with respect to ground (VSS) SR Injected input current on any pin during overload condition SR Absolute sum of all injected input currents during overload condition SR VDD slope to ensure correct power up6
-- Relative to VDD -- -- -- --
IINJPAD IINJSUM TVDD
TA C-Grade Part TJ C-Grade Part TA V-Grade Part TJ V-Grade Part TA M-Grade Part TJ M-Grade Part
1 2
SR Ambient temperature under bias SR Junction temperature under bias SR Ambient temperature under bias SR Junction temperature under bias SR Ambient temperature under bias SR Junction temperature under bias
fCPU < 64 MHz -- fCPU < 64 MHz -- fCPU < 60 MHz --
100 nF capacitance needs to be provided between each VDD/VSS pair. Full device operation is guaranteed by design when the voltage drops below 4.5V down to 3.6V. However, certain analog electrical characteristics will not be guaranteed to stay within the stated limits. 3 330 nF capacitance needs to be provided between each V DD_LV/VSS_LV supply pair.
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4 14 Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5604BxMG products in 208 MAPBGA packages
Electrical characteristics
4
470 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed depending on external regulator characteristics). 5 100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair. 6 Guaranteed by device validation
NOTE
RAM data retention is guaranteed with VDD_LV not below 1.08 V.
4.6
4.6.1
Thermal characteristics
Package thermal characteristics
Table 9. LQFP thermal characteristics1
Value3 Unit Min -- -- -- -- Typ -- -- -- -- Max 64 64 50.8 49.4 C/W
Symbol RJA CC
C D
Parameter Thermal resistance, junction-to-ambient natural convection4
Conditions2 Single-layer board--1s
Pin count 100 144
Four-layer board--2s2p
100 144
1 2
Thermal characteristics are targets based on simulation that are subject to change per device characterization. VDD = 3.3 V 10% / 5.0 V 10%, TA = -40 to 125 C. 3 All values need to be confirmed during device validation. 4 Junction-to-ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets JEDEC specification for this package. When Greek letters are not available, the symbols are typed as RthJA and RthJMA.
Table 10. 208 MAPBGA thermal characteristics1
Symbol C Parameter Conditions Value TBD Unit C/W
RJA CC -- Thermal resistance, junction-to-ambient natural Single-layer board--1s convection2 Four-layer board--2s2p
1 2
Thermal characteristics are targets based on simulation that are subject to change per device characterization. Junction-to-ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets JEDEC specification for this package. When Greek letters are not available, the symbols are typed as RthJA and RthJMA.
4.6.2
Power considerations
TJ = TA + (PD x RJA) Where: TA is the ambient temperature in C. RJA is the package junction-to-ambient thermal resistance, in C/W. PD is the sum of PINT and PI/O (PD = PINT + PI/O). Eqn. 1
The average chip-junction temperature, TJ, in degrees Celsius, may be calculated using Equation 1:
MPC5604B/C Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 15
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5604BxMG products in 208 MAPBGA packages
Electrical characteristics
PINT is the product of IDD and VDD, expressed in watts. This is the chip internal power. PI/O represents the power dissipation on input and output pins; user determined. Most of the time for the applications, PI/O < PINT and may be neglected. On the other hand, PI/O may be significant, if the device is configured to continuously drive external modules and/or memories. An approximate relationship between PD and TJ (if PI/O is neglected) is given by: PD = K / (TJ + 273 C) Therefore, solving equations 1 and 2: K = PD x (TA + 273 C) + RJA x PD2 Eqn. 3 Eqn. 2
Where: K is a constant for the particular part, which may be determined from Equation 3 by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ may be obtained by solving equations 1 and 2 iteratively for any value of TA.
4.7
4.7.1
* * * *
I/O pad electrical characteristics
I/O pad types
Slow pads--These pads are the most common pads, providing a good compromise between transition time and low electromagnetic emission. Medium pads--These pads provide transition fast enough for the serial communication channels with controlled current to reduce electromagnetic emission. Fast pads--These pads provide maximum speed. There are used for improved Nexus debugging capability. Input only pads--These pads are associated to ADC channels and 32 kHz slow external crystal oscillator providing low input leakage.
The device provides four main I/O pad types depending on the associated alternate functions:
Medium and Fast pads can use slow configuration to reduce electromagnetic emission, at the cost of reducing AC performance.
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4 16 Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5604BxMG products in 208 MAPBGA packages
Electrical characteristics
4.7.2
I/O input DC characteristics
Figure 5. I/O input DC electrical characteristics definition
VIN VDD VIH
Table 11 provides input DC electrical characteristics as described in Figure 5.
VHYS
VIL
PDIx = `1' (GPDI register of SIUL)
PDIx = `0'
Table 11. I/O input DC electrical characteristics
Symbol VIH VIL C Parameter Conditions1 Min SR P Input high level CMOS (Schmitt Trigger) SR P Input low level CMOS (Schmitt Trigger) -- -- -- No injection on adjacent pin TA = -40 C TA = 25 C TA = 105 C TA = 125 C -- -- 0.65VDD -0.4 0.1VDD -- -- -- -- -- 1000 Value2 Unit Typ -- -- -- 2 2 12 70 -- -- Max VDD+0.4 0.35VDD -- -- -- 500 1000 40 -- ns ns nA V
VHYS CC C Input hysteresis CMOS (Schmitt Trigger) ILKG CC P Digital input leakage P D P WFI
1 2
SR P Digital input filtered pulse
WNFI SR P Digital input not filtered pulse
VDD = 3.3 V 10% / 5.0 V 10%, TA = -40 to 125 C, unless otherwise specified All values need to be confirmed during device validation.
4.7.3
* *
I/O output DC characteristics
Table 12 provides weak pull figures. Both pull-up and pull-down resistances are supported. Table 13 provides output driver characteristics for I/O pads when in SLOW configuration.
MPC5604B/C Microcontroller Data Sheet, Rev. 4
The following tables provide DC characteristics for bidirectional pads:
Freescale Semiconductor
17
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5604BxMG products in 208 MAPBGA packages
Electrical characteristics
* *
Table 14 provides output driver characteristics for I/O pads when in MEDIUM configuration. Table 15 provides output driver characteristics for I/O pads when in FAST configuration. Table 12. I/O pull-up/pull-down DC electrical characteristics
Symbol
C
Parameter
Conditions1 Min VIN = VIL, VDD = 5.0 V 10% PAD3V5V = 0 PAD3V5V = 12 10 10 10 10 10 10
Value Unit Typ -- -- -- -- -- -- Max 150 250 150 150 250 150 A A
|IWPU| CC P Weak pull-up current absolute value C P |IWPD| CC P Weak pull-down current absolute value C P
1 2
VIN = VIL, VDD = 3.3 V 10% PAD3V5V = 1 VIN = VIH, VDD = 5.0 V 10% PAD3V5V = 0 PAD3V5V = 1 VIN = VIH, VDD = 3.3 V 10% PAD3V5V = 1
VDD = 3.3 V 10% / 5.0 V 10%, TA = -40 to 125 C, unless otherwise specified. The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
Table 13. SLOW configuration output buffer electrical characteristics
Symbol C Parameter Conditions1 Min VOH CC P Output high level SLOW configuration C C Push Pull IOH = -2 mA, VDD = 5.0 V 10%, PAD3V5V = 0 (recommended) IOH = -2 mA, VDD = 5.0 V 10%, PAD3V5V = 12 IOH = -1 mA, VDD = 3.3 V 10%, PAD3V5V = 1 (recommended) Push Pull IOL = 2 mA, VDD = 5.0 V 10%, PAD3V5V = 0 (recommended) IOL = 2 mA, VDD = 5.0 V 10%, PAD3V5V = 1(2) IOL = 1 mA, VDD = 3.3 V 10%, PAD3V5V = 1 (recommended) 0.8VDD Value Unit Typ -- Max -- V
0.8VDD VDD-0.8
-- --
-- --
VOL CC P Output low level SLOW configuration C
--
--
0.1VDD
V
--
--
0.1VDD
C
--
--
0.5
1 2
VDD = 3.3 V 10% / 5.0 V 10%, TA = -40 to 125 C, unless otherwise specified The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4 18 Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5604BxMG products in 208 MAPBGA packages
Electrical characteristics
Table 14. MEDIUM configuration output buffer electrical characteristics
Symbol C Parameter Conditions1 Min Push Pull IOH = -3.8 mA, VOH CC C Output high level MEDIUM configuration VDD = 5.0 V 10%, PAD3V5V = 0 P IOH = -2 mA, VDD = 5.0 V 10%, PAD3V5V = 0 (recommended) IOH = -1 mA, VDD = 5.0 V 10%, PAD3V5V = 12 IOH = -1 mA, VDD = 3.3 V 10%, PAD3V5V = 1 (recommended) IOH = -100 A, VDD = 5.0 V 10%, PAD3V5V = 0 0.8VDD 0.8VDD Value Unit Typ -- -- Max -- -- V
C C
0.8VDD VDD-0.8
-- --
-- --
C
0.8VDD -- --
-- -- --
-- 0.2VDD 0.1VDD V
VOL CC C Output low level Push Pull IOL = 3.8 mA, MEDIUM configuration VDD = 5.0 V 10%, PAD3V5V = 0 P IOL = 2 mA, VDD = 5.0 V 10%, PAD3V5V = 0 (recommended) IOL = 1 mA, VDD = 5.0 V 10%, PAD3V5V = 1(2) IOL = 1 mA, VDD = 3.3 V 10%, PAD3V5V = 1 (recommended) IOH = 100 A, VDD = 5.0 V 10%, PAD3V5V = 0
C C
-- --
-- --
0.1VDD 0.5
C
1 2
--
--
0.1VDD
VDD = 3.3 V 10% / 5.0 V 10%, TA = -40 to 125 C, unless otherwise specified The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
MPC5604B/C Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 19
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5604BxMG products in 208 MAPBGA packages
Electrical characteristics
Table 15. FAST configuration output buffer electrical characteristics
Symbol C Parameter Push Pull Conditions1 Min VOH CC P Output high level FAST configuration C C IOH = -14mA, VDD = 5.0 V 10%, PAD3V5V = 0 (recommended) IOH = -7mA, VDD = 5.0 V 10%, PAD3V5V = 12 IOH = -11mA, VDD = 3.3 V 10%, PAD3V5V = 1 (recommended) Push Pull IOL = 14mA, VDD = 5.0 V 10%, PAD3V5V = 0 (recommended) IOL = 7mA, VDD = 5.0 V 10%, PAD3V5V = 1(2) IOL = 11mA, VDD = 3.3 V 10%, PAD3V5V = 1 (recommended) 0.8VDD Value Unit Typ -- Max -- V
0.8VDD VDD-0.8
-- --
-- --
VOL CC P Output low level FAST configuration C C
--
--
0.1VDD
V
-- --
-- --
0.1VDD 0.5
1 2
VDD = 3.3 V 10% / 5.0 V 10%, TA = -40 to 125 C, unless otherwise specified The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
4.7.4
Output pin transition times
Table 16. Output pin transition times
Value2 Unit Min Typ -- -- -- -- -- -- -- -- -- -- -- -- Max 50 100 125 50 100 125 10 20 40 12 25 40 ns ns -- -- -- VDD = 3.3 V 10%, PAD3V5V = 1 -- -- -- VDD = 5.0 V 10%, PAD3V5V = 0 SIUL.PCRx.SRC = 1 VDD = 3.3 V 10%, PAD3V5V = 1 SIUL.PCRx.SRC = 1 -- -- -- -- -- --
Symbol
C
Parameter
Conditions1 CL = 25 pF CL = 50 pF CL = 100 pF CL = 25 pF CL = 50 pF CL = 100 pF pin(3) CL = 25 pF CL = 50 pF CL = 100 pF CL = 25 pF CL = 50 pF CL = 100 pF VDD = 5.0 V 10%, PAD3V5V = 0
Ttr CC D Output transition time output pin3 SLOW configuration T D D T D Ttr CC D Output transition time output MEDIUM configuration T D D T D
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4 20 Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5604BxMG products in 208 MAPBGA packages
Electrical characteristics
Table 16. Output pin transition times (continued)
Symbol C Parameter Conditions
1
Value2 Unit Min Typ -- -- -- -- -- -- Max 4 6 12 4 7 12 ns -- -- --
Ttr CC D Output transition time output pin(3) CL = 25 pF FAST configuration CL = 50 pF CL = 100 pF CL = 25 pF CL = 50 pF CL = 100 pF
1 2
VDD = 5.0 V 10%, PAD3V5V = 0
VDD = 3.3 V 10%, PAD3V5V = 1
-- -- --
VDD = 3.3 V 10% / 5.0 V 10%, TA = -40 to 125 C, unless otherwise specified All values need to be confirmed during device validation. 3 C includes device and package capacitances (C L PKG < 5 pF).
4.7.5
I/O pad current specification
The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is associated to a VDD/VSS supply pair as described in Table 17. Table 18 provides I/O consumption figures. In order to ensure device reliability, the average current of the I/O on a single segment should remain below the IAVGSEG maximum value. In order to ensure device functionality, the sum of the dynamic and static current of the I/O on a single segment should remain below the IDYNSEG maximum value. Table 17. I/O supply segment
Supply segment Package 1 208 MAPBGA1 144 LQFP 100 LQFP
1
2
3
4
5 MCKO -- --
6 MDOn/MSEO -- --
Equivalent to 144 LQFP segment pad distribution pin20-pin49 pin16-pin35 pin51-pin99 pin37-pin69 pin100-pin122 pin 123-pin19 pin70-pin83 pin 84-pin15
208 MAPBGA available only as development package for Nexus2+
MPC5604B/C Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 21
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5604BxMG products in 208 MAPBGA packages
Electrical characteristics
Table 18. I/O consumption
Symbol IDYNSEG C Parameter Conditions1 Min SR D Sum of all the dynamic and static I/O current within a supply segment CC D Dynamic I/O current for SLOW configuration VDD = 5.0 V 10%, PAD3V5V = 0 VDD = 3.3 V 10%, PAD3V5V = 1 -- -- Value2 Unit Typ -- -- Max 110 65 mA
ISWTSLW,3
CL = 25 pF
VDD = 5.0 V 10%, PAD3V5V = 0 VDD = 3.3 V 10%, PAD3V5V = 1 VDD = 5.0 V 10%, PAD3V5V = 0 VDD = 3.3 V 10%, PAD3V5V = 1 VDD = 5.0 V 10%, PAD3V5V = 0 VDD = 3.3 V 10%, PAD3V5V = 1 VDD = 5.0 V 10%, PAD3V5V = 0
-- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
20 16 29 17 110 50 2.3 3.2 6.6 1.6 2.3 4.7 6.6 13.4 18.3 5 8.5 11 22 33 56 14 20 35 70 65
mA
ISWTMED(3)
CC D Dynamic I/O current CL = 25 pF for MEDIUM configuration
mA
ISWTFST(3)
CC D Dynamic I/O current CL = 25 pF for FAST configuration
mA
IRMSSLW
CC D Root medium square CL = 25 pF, 2 MHz I/O current for SLOW CL = 25 pF, 4 MHz configuration CL = 100 pF, 2 MHz CL = 25 pF, 2 MHz CL = 25 pF, 4 MHz CL = 100 pF, 2 MHz
mA
VDD = 3.3 V 10%, PAD3V5V = 1
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
IRMSMED
CC D Root medium square CL = 25 pF, 13 MHz VDD = 5.0 V 10%, I/O current for PAD3V5V = 0 CL = 25 pF, 40 MHz MEDIUM configuration CL = 100 pF, 13 MHz CL = 25 pF, 13 MHz CL = 25 pF, 40 MHz CL = 100 pF, 13 MHz VDD = 3.3 V 10%, PAD3V5V = 1
mA
IRMSFST
CC D Root medium square CL = 25 pF, 40 MHz VDD = 5.0 V 10%, I/O current for FAST PAD3V5V = 0 CL = 25 pF, 64 MHz configuration CL = 100 pF, 40 MHz CL = 25 pF, 40 MHz CL = 25 pF, 64 MHz CL = 100 pF, 40 MHz VDD = 3.3 V 10%, PAD3V5V = 1
mA
IAVGSEG
SR D Sum of all the static I/O current within a supply segment
VDD = 5.0 V 10%, PAD3V5V = 0 VDD = 3.3 V 10%, PAD3V5V = 1
mA
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4 22 Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5604BxMG products in 208 MAPBGA packages
Electrical characteristics VDD = 3.3 V 10% / 5.0 V 10%, TA = -40 to125 C, unless otherwise specified All values need to be confirmed during device validation. 3 Stated maximum values represent peak consumption that lasts only a few ns during I/O transition.
1 2
4.8
nRSTIN electrical characteristics
Figure 6. Start-up reset requirements
VDD VDDMIN
The device implements a dedicated bidirectional RESET pin.
nRSTIN
VIH VIL device reset forced by nRSTIN device start-up phase
Figure 7. Noise filtering on reset signal
VRSTIN hw_rst
VDD
`1'
VIH
VIL
`0'
filtered by hysteresis filtered by lowpass filter WFRST filtered by lowpass filter WFRST WNFRST unknown reset state device under hardware reset
MPC5604B/C Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 23
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Electrical characteristics
Table 19. Reset electrical characteristics
Symbol VIH VIL VHYS VOL C Parameter Conditions1 Min SR P Input High Level CMOS (Schmitt Trigger) SR P Input low Level CMOS (Schmitt Trigger) CC C Input hysteresis CMOS (Schmitt Trigger) CC P Output low level -- -- -- Push Pull, IOL = 2mA, VDD = 5.0 V 10%, PAD3V5V = 0 (recommended) Push Pull, IOL = 1mA, VDD = 5.0 V 10%, PAD3V5V = 13 Push Pull, IOL = 1mA, VDD = 3.3 V 10%, PAD3V5V = 1 (recommended) Ttr CC D Output transition time output pin4 MEDIUM configuration CL = 25pF, VDD = 5.0 V 10%, PAD3V5V = 0 CL = 50pF, VDD = 5.0 V 10%, PAD3V5V = 0 CL = 100pF, VDD = 5.0 V 10%, PAD3V5V = 0 CL = 25pF, VDD = 3.3 V 10%, PAD3V5V = 1 CL = 50pF, VDD = 3.3 V 10%, PAD3V5V = 1 CL = 100pF, VDD = 3.3 V 10%, PAD3V5V = 1 WFRST SR P nRSTIN input filtered pulse WNFRST SR P nRSTIN input not filtered pulse |IWPU| CC P Weak pull-up current absolute value -- -- VDD = 3.3 V 10%, PAD3V5V = 1 VDD = 5.0 V 10%, PAD3V5V = 0 VDD = 5.0 V 10%, PAD3V5V = 15
1 2
Value2 Unit Typ -- -- -- -- Max VDD+0.4 0.35VDD -- 0.1VDD V V V V 0.65VDD -0.4 0.1VDD --
-- --
-- --
0.1VDD 0.5
-- -- -- -- -- -- -- 1000 10 10 10
-- -- -- -- -- -- -- -- -- -- --
10 20 40 12 25 40 40 -- 150 150 250
ns
ns ns A
VDD = 3.3 V 10% / 5.0 V 10%, TA = -40 to 125 C, unless otherwise specified All values need to be confirmed during device validation. 3 This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to RGM module section of the device reference manual). 4 CL includes device and package capacitance (CPKG < 5 pF). 5 The configuration PAD3V5 = 1 when V DD = 5 V is only transient configuration during power-up. All pads but RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4 24 Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5604BxMG products in 208 MAPBGA packages
Electrical characteristics
4.9
4.9.1
Power management electrical characteristics
Voltage regulator electrical characteristics
The device implements an internal voltage regulator to generate the low voltage core supply VDD_LV from the high voltage ballast supply VDD_BV. The regulator itself is supplied by the common I/O supply VDD. The following supplies are involved: * * * HV--High voltage external power supply for voltage regulator module. This must be provided externally through VDD power pin. BV--High voltage external power supply for internal ballast module. This must be provided externally through VDD_BV power pin. Voltage values should be aligned with VDD. LV--Low voltage internal power supply for core, FMPLL and flash digital logic. This is generated by the internal voltage regulator but provided outside to connect stability capacitor. It is further split into four main domains to ensure noise isolation between critical LV modules within the device: -- LV_COR--Low voltage supply for the core. It is also used to provide supply for FMPLL through double bonding. -- LV_CFLA--Low voltage supply for code flash module. It is supplied with dedicated ballast and shorted to LV_COR through double bonding. -- LV_DFLA--Low voltage supply for data flash module. It is supplied with dedicated ballast and shorted to LV_COR through double bonding. -- LV_PLL--Low voltage supply for FMPLL. It is shorted to LV_COR through double bonding. Figure 8. Voltage regulator capacitance connection
CREG2 (LV_COR/LV_CFLA) GND VDD VSS_LV VDD_LV
VDD_BV VREF CDEC1 (Ballast decoupling) CREG1 (LV_COR/LV_DFLA)
VDD_BV
VDD_LV
VDD_LVn Voltage Regulator
DEVICE
I
VSS_LV VSS_LV VDD_LV VSS VDD
VSS_LVn
GND
DEVICE
GND
GND CREG3 (LV_COR/LV_PLL) CDEC2 (supply/IO decoupling)
The internal voltage regulator requires external capacitance (CREGn) to be connected to the device in order to provide a stable low voltage digital supply to the device. Capacitances should be placed on the board as near as possible to the associated pins. Care should also be taken to limit the serial inductance of the board to less than 5 nH.
MPC5604B/C Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 25
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Electrical characteristics
Each decoupling capacitor must be placed between each of the three VDD_LV/VSS_LV supply pairs to ensure stable voltage (see Section 4.5, "Recommended operating conditions). Table 20. Voltage regulator electrical characteristics
Symbol CREGn RREG CDEC1 CDEC2 VMREG C Parameter Conditions1 Min SR -- Internal voltage regulator external capacitance SR -- Stability capacitor equivalent serial resistance SR -- Decoupling capacitance3 ballast SR -- Decoupling capacitance regulator supply CC P Main regulator output voltage -- -- VDD_BV/VSS_LV pair VDD/VSS pair Before trimming After trimming IMREG IMREGINT SR -- Main regulator current provided to VDD_LV domain CC D Main regulator module current consumption CC P Low power regulator output voltage SR -- Low power regulator current provided to VDD_LV domain -- IMREG = 200 mA IMREG = 0 mA After trimming -- 200 -- 400 10 -- -- -- -- -- -- -- -- -- -- -- -- -- -- Value2 Unit Typ -- -- 4704 100 1.32 1.28 -- -- -- 1.23 -- -- 5 1.23 -- -- 2 17 Max 330 0.2 -- -- -- -- 150 2 1 -- 15 600 TBD -- 5 100 TBD -- A V mA A V mA A mA mA nF nF nF V
VLPREG ILPREG ILPREGINT
CC D Low power regulator module current ILPREG = 15 mA; consumption TA = 55 C -- ILPREG = 0 mA; TA = 55 C Post trimming -- IULPREG = 5 mA; TA = 55 C IULPREG = 0 mA; TA = 55 C
VULPREG IULPREG IULPREGINT
CC P Ultra low power regulator output voltage SR -- Ultra low power regulator current provided to VDD_LV domain CC D Ultra low power regulator module current consumption
IVREGREF
CC D Main LVDs and reference current consumption (low power and main regulator switched off) CC D Main LVD current consumption (switch-off during standby) CC D In-rush current on VDD_BV during power-up
TA = 55 C
IVREDLVD12 IDD_BV
1 2
TA = 55 C --
-- --
2 --
TBD 4005
A mA
VDD = 3.3 V 10% / 5.0 V 10%, TA = -40 to 125 C, unless otherwise specified All values need to be confirmed during device validation.
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4 26 Freescale Semiconductor
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Electrical characteristics
3
This capacitance value is driven by the constraints of the external voltage regulator supplying the VDD_BV voltage. A typical value is in the range of 470 nF. 4 External regulator and capacitance circuitry must be capable of providing IDD_BV while maintaining supply VDD_BV in operating range. 5 In-rush current is seen only for short time during power-up and on standby exit (max 20s, depending on external capacitances to be load)
4.9.2
Voltage monitor electrical characteristics
The device implements a Power-on Reset (POR) module to ensure correct power-up initialization, as well as four low voltage detectors (LVDs) to monitor the VDD and the VDD_LV voltage while device is supplied: * * * * * POR monitors VDD during the power-up phase to ensure device is maintained in a safe reset state LVDHV3 monitors VDD to ensure device reset below minimum functional supply LVDHV5 monitors VDD when application uses device in the 5.0 V 10% range LVDLVCOR monitors power domain No. 1 LVDLVBKP monitors power domain No. 0
NOTE
When enabled, power domain No. 2 is monitored through LVD_DIGBKP. Figure 9. Low voltage monitor vs reset
VDD
VLVDHVxH VLVDHVxL
RESET
MPC5604B/C Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 27
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5604BxMG products in 208 MAPBGA packages
Electrical characteristics
Table 21. Low voltage monitor electrical characteristics
Symbol VPORUP VPORH VLVDHV3H VLVDHV3L VLVDHV5H VLVDHV5L C Parameter Conditions1 Min SR P Supply for functional POR module CC P Power-on reset threshold CC T LVDHV3 low voltage detector high threshold CC P LVDHV3 low voltage detector low threshold CC T LVDHV5 low voltage detector high threshold CC P LVDHV5 low voltage detector low threshold TA = 25 C, after trimming 1.0 1.5 -- 2.7 -- 3.8 1.07 1.07 Value2 Unit Typ -- -- -- -- -- -- -- -- Max 5.5 2.6 2.95 2.9 4.5 4.4 1.11 1.11 V
VLVDLVCORL CC P LVDLVCOR low voltage detector low threshold VLVDLVBKPL CC P LVDLVBKP low voltage detector low threshold
1 2
VDD = 3.3 V 10% / 5.0 V 10%, TA = -40 to 125 C, unless otherwise specified All values need to be confirmed during device validation.
4.10
Low voltage domain power consumption
Table 22. Low voltage power domain electrical characteristics
Symbol IDDMAX2 IDDRUN4 C Parameter Conditions1 Min CC D RUN mode maximum average current CC T RUN mode typical average current5 P CC P HALT mode CC P STOP mode D D D P current6 current7 -- -- -- -- Slow internal RC oscillator TA = 25 C (128 kHz) running TA = 55 C TA = 85 C TA = 105 C TA = 125 C -- -- -- -- -- -- -- -- -- -- -- -- -- -- Value Unit Typ 115 60 TBD 8 180 500 1 2 4.5 30 TBD Max 1403 80 TBD TBD 7008 -- -- -- TBD(8) 100 -- -- -- TBD A mA mA A mA mA
Table 22 provides DC electrical characteristics for significant application modes. These values are indicative values; actual consumption depends on the application.
IDDHALT IDDSTOP
IDDSTDBY2
CC P STANDBY2 mode current9 Slow internal RC oscillator TA = 25 C (128 kHz) running D TA = 55 C D D P TA = 85 C TA = 105 C TA = 125 C
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4 28 Freescale Semiconductor
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Electrical characteristics
Table 22. Low voltage power domain electrical characteristics (continued)
Symbol IDDSTDBY1 C Parameter Conditions1 Min CC T STANDBY1 mode current10 D D D D
1 2
Value Unit Typ 20 TBD Max 60 -- -- -- 280 TBD A -- -- -- -- --
Slow internal RC oscillator TA = 25 C (128 kHz) running TA = 55 C TA = 85 C TA = 105 C TA = 125 C
VDD = 3.3 V 10% / 5.0 V 10%, TA = -40 to 125 C, unless otherwise specified Running consumption is given on voltage regulator supply (VDDREG). It does not include consumption linked to I/Os toggling. This value is highly dependent on the application. The given value is thought to be a worst case value with all peripherals running, and code fetched from code flash while modify operation on-going on data flash. It is to be noticed that this value can be significantly reduced by application: switch-off not used peripherals (default), reduce peripheral frequency through internal prescaler, fetch from RAM most used functions, use low power mode when possible. 3 Higher current may be sinked by device during power-up and standby exit. please refer to in rush current on Table 20. 4 RUN current measured with typical application with accesses on both flash and RAM. 5 Only for the "P" classification: Code fetched from RAM: Serial IPs CAN and LIN in loop back mode, DSPi as Master, PLL as system Clock (4 x Multiplier) peripherals on (eMIOS/CTU/ADC) and running at max frequency, periodic SW/WDG timer reset enabled. 6 Data Flash Power Down. Code Flash in Low Power. RC-osc128kHz & RC-OSC 16MHz on. 10MHz XTAL clock. FlexCAN: instances: 0, 1, 2 ON (clocked but not reception or transmission), instances: 4, 5, 6 clock gated. LINFlex: instances: 0, 1, 2 ON (clocked but not reception or transmission), instance: 3 clock gated. eMIOS: instance: 0 ON (16 channels on PA[0]-PA[11] and PC[12]-PC[15]) with PWM 20KHz, instance: 1 clock gated. DSPI: instance: 0 (clocked but no communication). RTC/API ON.PIT ON. STM ON. ADC ON but not conversion except 2 analogue watchdog 7 Only for the "P" classification: No clock, RC 16MHz off, RC128kHz on, PLL off, HPvreg off, ULPVreg/LPVreg on. All possible peripherals off and clock gated. Flash in power down mode. 8 When going from RUN to STOP mode and the core consumption is > 6 mA , it is normal operation for the main regulator module to be kept on by the on-chip current monitoring circuit. This is most likely to occur with junction temperatures exceeding 125 C and under these circumstances , it is possible for the current to initially exceed the maximum STOP specification by up to 2 mA. After entering stop, the application junction temperature will reduce to the ambient level and the main regulator will be automatically switched off when the load current is below 6 mA. 9 Only for the "P" classification: ULPreg on, HP/LPVreg off, 32kB RAM on, device configured for minimum consumption, all possible modules switched-off. 10 ULPreg on, HP/LPVreg off, 8kB RAM on, device configured for minimum consumption, all possible modules switched-off.
4.11
4.11.1
Flash memory electrical characteristics
Program/Erase characteristics
Table 23 shows the program and erase characteristics.
MPC5604B/C Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 29
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Electrical characteristics
Table 23. Program and erase specifications
Value Symbol C Parameter Min Tdwprogram CC C Double word (64 bits) program time4 T16Kpperase T32Kpperase T128Kpperase
1
Typ1 22 300 400 800
Initial max2 TBD 500 600 1300
Max3 500 5000 5000 7500
Unit
-- -- -- --
s ms ms ms
16 KB block pre-program and erase time 32 KB block pre-program and erase time 128 KB block pre-program and erase time
Typical program and erase times assume nominal supply values and operation at 25 C. All times are subject to change pending device characterization. 2 Initial factory condition: < 100 program/erase cycles, 25 C, typical supply voltage. 3 The maximum program and erase times occur after the specified number of program/erase cycles. These maximum values are characterized but not guaranteed. 4 Actual hardware programming times. This does not include software overhead.
Table 24. Flash module life
Value Symbol P/E C Parameter Conditions Min CC C Number of program/erase cycles per block for 16 Kbyte blocks over the operating temperature range (TJ) CC C Number of program/erase cycles per block for 32 Kbyte blocks over the operating temperature range (TJ) CC C Number of program/erase cycles per block for 128 Kbyte blocks over the operating temperature range (TJ) -- 100,000 Typ -- cycles Unit
P/E
--
10,000
100,0001 cycles
P/E
--
1,000
100,000(1) cycles
Retention CC C Minimum data retention at 85 C average ambient temperature2
Blocks with 0-1,000 P/E cycles Blocks with 10,000 P/E cycles Blocks with 100,000 P/E cycles
20 10 1-5
-- -- --
years years years
1 2
To be confirmed Ambient temperature averaged over duration of application, not to exceed recommended product operating temperature range.
ECC circuitry provides correction of single bit faults and is used to improve further automotive reliability results. Some units will experience single bit corrections throughout the life of the product with no impact to product reliability.
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4 30 Freescale Semiconductor
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Electrical characteristics
Table 25. Flash read access timing
Symbol fREAD C Parameter Conditions1 2 wait states 1 wait state 0 wait states Max 64 40 20 Unit MHz
CC P Maximum frequency for Flash reading C C
1
VDD = 3.3 V 10% / 5.0 V 10%, TA = -40 to 125 C, unless otherwise specified
4.11.2
Flash power supply DC characteristics
Table 26. Flash power supply DC electrical characteristics
Table 26 shows the power supply DC characteristics on external supply.
Symbol
C
Parameter
Conditions1 Min -- --
Value2 Unit Typ -- -- Max 33 33 mA mA
IFREAD CC D Sum of the current consumption on VDDHV Flash module read fCPU = 64 MHz3 and VDDBV on read access IFMOD CC D Sum of the current consumption on VDDHV Program/Erase on-going and VDDBV on matrix modification while reading Flash registers (program/erase) fCPU = 64 MHz(3) CC D Sum of the current consumption on VDDHV and VDDBV during Flash low-power mode CC D Sum of the current consumption on VDDHV and VDDBV during Flash powe-down mode
IFLPW IFPWD
1 2
-- --
-- --
900 150
A A
VDD = 3.3 V 10% / 5.0 V 10%, TA = -40 to 125 C, unless otherwise specified All values need to be confirmed during device validation. 3f CPU 64 MHz can be achieved only at up to 105 C
4.11.3
Start-up/Switch-off timings
Table 27. Start-up time/Switch-off time
Symbol C Parameter Conditions1 Min -- -- -- -- -- -- -- -- -- -- Value Unit Typ -- -- -- -- -- Max 125 0.5 30 0.5 1.5 s
TFLARSTEXIT TFLALPEXIT TFLAPDEXIT
CC T Delay for Flash module to exit reset mode CC T Delay for Flash module to exit low-power mode CC T Delay for Flash module to exit power-down mode
TFLALPENTRY CC T Delay for Flash module to enter low-power mode TFLAPDENTRY CC T Delay for Flash module to enter power-down mode
MPC5604B/C Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 31
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Electrical characteristics
1
VDD = 3.3 V 10% / 5.0 V 10%, TA = -40 to 125 C, unless otherwise specified
4.12
Electromagnetic compatibility (EMC) characteristics
Susceptibility tests are performed on a sample basis during product characterization.
4.12.1
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user apply EMC software optimization and prequalification tests in relation with the EMC level requested for his application. * Software recommendations - The software flowchart must include the management of runaway conditions such as: -- Corrupted program counter -- Unexpected reset -- Critical data corruption (control registers...) Prequalification trials - Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the reset pin or the oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring.
*
4.12.2
Electromagnetic interference (EMI)
The product is monitored in terms of emission based on a typical application. This emission test conforms to the IEC 61967-1 standard, which specifies the general conditions for EMI measurements. Table 28. EMI radiated emission measurement1,2
Value Symbol -- fCPU C Parameter Conditions Min S -- Scan range R S -- Operating frequency R -- -- -- No PLL frequency VDD = 5 V, TA = 25 C, modulation LQFP144 package Test conforming to IEC 61967-2, 2% PLL fOSC = 8 MHz/fCPU = 64 MHz frequency modulation 0.15 0 -- -- -- -- 64 1.28 -- -- Typ Max 1000 MHz -- -- 18 143 MHz V dB V dB V Unit
VDD_L S -- LV operating R voltages V SEMI C T Peak level C
1 2
EMI testing and I/O port waveforms per IEC 61967-1, -2, -4 For information on conducted emission and susceptibility measurement (norm IEC 61967-4), please contact your local marketing representative. 3 All values need to be confirmed during device validation
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4 32 Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5604BxMG products in 208 MAPBGA packages
Electrical characteristics
4.12.3
Absolute maximum ratings (electrical sensitivity)
Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity.
4.12.3.1
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This test conforms to the AEC-Q100-002/-003/-011 standard. Table 29. ESD absolute maximum ratings1 2
Symbol C Ratings Conditions TA = 25 C conforming to AEC-Q100-002 TA = 25 C conforming to AEC-Q100-003 TA = 25 C conforming to AEC-Q100-011 Class H1C M2 C3A Max value 2000 200 500 750 (corners) Unit V
VESD(HBM) CC T Electrostatic discharge voltage (Human Body Model) VESD(MM) CC T Electrostatic discharge voltage (Machine Model) VESD(CDM) CC T Electrostatic discharge voltage (Charged Device Model)
1
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. 2 A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification requirements. Complete DC parametric and functional testing shall be performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification.
4.12.3.2
* *
Static latch-up (LU)
Two complementary static tests are required on six parts to assess the latch-up performance: A supply overvoltage is applied to each power supply pin. A current injection is applied to each input, output and configurable I/O pin. Table 30. Latch-up results
Symbol LU CC C Parameter Conditions TA = 125 C conforming to JESD 78 Class II level A
These tests are compliant with the EIA/JESD 78 IC latch-up standard.
T Static latch-up class
4.13
Fast external crystal oscillator (4 to 16 MHz) electrical characteristics
The device provides an oscillator/resonator driver. Figure 10 describes a simple model of the internal oscillator driver and provides an example of a connection for an oscillator or a resonator.
MPC5604B/C Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 33
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Electrical characteristics
Table 31 provides the parameter description of 4 MHz to 16 MHz crystals used for the design simulations. Figure 10. Crystal oscillator and resonator connection scheme
EXTAL C1 Crystal EXTAL
XTAL
DEVICE
VDD
C2
I
R
EXTAL XTAL Resonator
DEVICE
XTAL
DEVICE
NOTE
XTAL/EXTAL must not be directly used to drive external circuits.
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4 34 Freescale Semiconductor
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Electrical characteristics
Table 31. Crystal description
Crystal equivalent series resistance ESR 300 300 150 120 120 Crystal motional capacitance (Cm) fF 2.68 2.46 2.93 3.11 3.90 Crystal motional inductance (Lm) mH 591.0 160.7 86.6 56.5 25.3 Load on xtalin/xtalout C1 = C2 (pF)1 21 17 15 15 10 Shunt capacitance between xtalout and xtalin C02 (pF) 2.93 3.01 2.91 2.93 3.00
Nominal frequency (MHz)
NDK crystal reference
4 8 10 12 16
1
NX8045GB NX5032GA
The values specified for C1 and C2 are the same as used in simulations. It should be ensured that the testing includes all the parasitics (from the board, probe, crystal, etc.) as the AC / transient behavior depends upon them. 2 The value of C0 specified here includes 2 pF additional capacitance for parasitics (to be seen with bond-pads, package, etc.).
Figure 11. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics
S_MTRANS bit (ME_GS register) `1'
`0' VXTAL VFXOSC VFXOSCOP 10% TFXOSCSU valid internal clock
1/fFXOSC 90%
MPC5604B/C Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 35
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Electrical characteristics
Table 32. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics
Symbol fFXOSC gmFXOSC C Parameter Conditions1 Min SR -- Fast external crystal oscillator frequency CC C Fast external crystal oscillator transconductance CC P -- VDD = 3.3 V 10%, PAD3V5V = 1 OSCILLATOR_MARGIN = 0 VDD = 5.0 V 10%, PAD3V5V = 0 OSCILLATOR_MARGIN = 0 VDD = 3.3 V 10%, PAD3V5V = 1 OSCILLATOR_MARGIN = 1 VDD = 5.0 V 10%, PAD3V5V = 0 OSCILLATOR_MARGIN = 1 fOSC = 4 MHz, OSCILLATOR_MARGIN = 0 fOSC = 16 MHz, OSCILLATOR_MARGIN = 1 VFXOSCOP CC P Oscillation operating point IFXOSC,3 TFXOSCSU CC T Fast external crystal oscillator consumption CC T Fast external crystal oscillator start-up time -- -- fOSC = 4 MHz, OSCILLATOR_MARGIN = 0 fOSC = 16 MHz, OSCILLATOR_MARGIN = 1 VIH VIL
1 2
Value2 Unit Typ -- -- Max 16.0 8.2 MHz mA/V 4.0 2.2
2.0
--
7.4
CC C
2.7
--
9.7
CC C
2.5
--
9.2
VFXOSC
CC T Oscillation amplitude at EXTAL
1.3 1.3 -- -- -- -- 0.65VDD -0.4
-- -- 0.95 2 -- -- -- --
-- --
V
V 3 6 1.8 VDD+0.4 0.35VDD V V mA ms
SR P Input high level CMOS (Schmitt Trigger) SR P Input low level CMOS (Schmitt Trigger)
Oscillator bypass mode Oscillator bypass mode
VDD = 3.3 V 10% / 5.0 V 10%, TA = -40 to 125 C, unless otherwise specified All values need to be confirmed during device validation. 3 Stated values take into account only analog module consumption but not the digital contributor (clock tree and enabled peripherals)
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4 36 Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5604BxMG products in 208 MAPBGA packages
Electrical characteristics
4.14
Slow external crystal oscillator (32 kHz) electrical characteristics
Figure 12. Crystal oscillator and resonator connection scheme
The device provides a low power oscillator/resonator driver.
OSC32K_EXTAL C1
OSC32K_EXTAL Resonator
OSC32K_XTAL
OSC32K_XTAL C2
DEVICE
DEVICE
NOTE
OSC32K_XTAL/OSC32K_EXTAL must not be directly used to drive external circuits. Figure 13. Equivalent circuit of a quartz crystal
C0
C1
Crystal
C2 C1
Cm
Rm
Lm C2
MPC5604B/C Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 37
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Crystal
Electrical characteristics
Table 33. Crystal motional characteristics1
Value Symbol Lm Cm Parameter Motional inductance Motional capacitance Conditions Min -- -- -- AC coupled @ C0 = 2.85 pF4 AC coupled @ C0 = 4.9 pF
(4)
Unit Typ 11.796 2 -- -- -- -- -- Max -- -- 28 65 50 35 30 KH fF pF kW -- -- 18 -- -- -- --
C1/C2 Load capacitance at OSC32K_XTAL and OSC32K_EXTAL with respect to ground2 Rm3 Motional resistance
AC coupled @ C0 = 7.0 pF(4) AC coupled @ C0 = 9.0 pF
1 2 (4)
The crystal used is Epson Toyocom MC306. This is the recommended range of load capacitance at OSC32K_XTAL and OSC32K_EXTAL with respect to ground. It includes all the parasitics due to board traces, crystal and package. 3 Maximum ESR (R ) of the crystal is 50 k m 4 C0 Includes a parasitic capacitance of 2.0 pF between OSC32K_XTAL and OSC32K_EXTAL pins
Figure 14. Slow external crystal oscillator (32 kHz) electrical characteristics
OSCON bit (OSC_CTL register) 1
0
VOSC32K_XTAL VSXOSC 90%
1/fSXOSC
10% TSXOSCSU valid internal clock
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4 38 Freescale Semiconductor
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Electrical characteristics
Table 34. Slow external crystal oscillator (32 kHz) electrical characteristics
Symbol fSXOSC gmSXOSC C Parameter Conditions1 Min SR -- Slow external crystal oscillator frequency CC -- Slow external crystal oscillator transconductance -- VDD = 3.3 V 10%, PAD3V5V = 1 VDD = 5.0 V 10% PAD3V5V = 0 VDD = 3.3 V 10%, PAD3V5V = 1 VDD = 5.0 V 10%, PAD3V5V = 0 VSXOSC CC T Oscillation amplitude -- -- -- -- -- -- -- 32 Value2 Unit Typ 32.768 TBD TBD TBD TBD 2.1 TBD -- -- 8 23 -- V A A s Max 40 kHz mA/V
ISXOSCBIAS CC T Oscillation bias current ISXOSC TSXOSCSU
1 2
CC T Slow external crystal oscillator consumption CC T Slow external crystal oscillator start-up time
VDD = 3.3 V 10% / 5.0 V 10%, TA = -40 to 125 C, unless otherwise specified All values need to be confirmed during device validation. 3 Start-up time has been measured with EPSON TOYOCOM MC306 crystal. Variation may be seen with other crystal
4.15
FMPLL electrical characteristics
Table 35. FMPLL electrical characteristics
Symbol fPLLIN C Parameter Conditions1 Min SR -- FMPLL reference clock3 SR -- FMPLL reference clock duty cycle(3) -- -- -- -- -- Stable oscillator (fPLLIN = 16 MHz) fPLLIN = 16 MHz (resonator), fPLLCLK @ 64 MHz, 4000 cycles TA = 25 C -- -- 4 40 16 -- 20 Value2 Unit Typ -- -- -- -- -- 40 -- -- Max 64 60 64 644 150 100 10 4 MHz % MHz MHz MHz s ns mA
The device provides a frequency-modulated phase-locked loop (FMPLL) module to generate a fast system clock from the main oscillator driver.
PLLIN
fPLLOUT CC P FMPLL output clock frequency fCPU fFREE tLOCK SR -- System clock frequency CC P Free-running frequency CC P FMPLL lock time
tLTJIT CC -- FMPLL long term jitter IPLL
1
CC C FMPLL consumption
VDD = 3.3 V 10% / 5.0 V 10%, TA = -40 to 125 C, unless otherwise specified.
MPC5604B/C Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 39
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Electrical characteristics
2 3
All values need to be confirmed during device validation. PLLIN clock retrieved directly from FXOSC clock. Input characteristics are granted when oscillator is used in functional mode. When bypass mode is used, oscillator input clock should verify fPLLIN and PLLIN. 4 fCPU 64 MHz can be achieved only at up to 105 C
4.16
Fast internal RC oscillator (16 MHz) electrical characteristics
Table 36. Fast internal RC oscillator (16 MHz) electrical characteristics
Symbol fFIRC C Parameter Conditions1 Min CC P Fast internal RC oscillator high TA = 25 C, trimmed frequency SR -- -- -- 12 -- -- Value2 Unit Typ 16 Max -- 20 200 A MHz
The device provides a 16 MHz fast internal RC oscillator. This is used as the default clock at the power-up of the device.
IFIRCRUN3, CC T Fast internal RC oscillator high TA = 25 C, trimmed frequency current in running mode IFIRCPWD CC D Fast internal RC oscillator high TA = 25 C frequency current in power -- TA = 55 C down mode sysclk = off sysclk = 2 MHz sysclk = 4 MHz sysclk = 8 MHz sysclk = 16 MHz TFIRCSU CC C Fast internal RC oscillator start-up time -- -- -- FIRCPRE CC C Fast internal RC oscillator precision after software trimming of fFIRC TA = 25 C TA = 55 C VDD = 5.0 V 10% VDD = 3.3 V 10% TA = 125 C VDD = 5.0 V 10% VDD = 3.3 V 10%
-- -- -- -- -- -- -- -- -- -- -- -1
TBD TBD 500 600 700 900 1250 1.1 1.2 -- -- --
10 TBD -- -- -- -- -- 2.0 TBD 2.0 TBD +1
A
IFIRCSTOP CC T Fast internal RC oscillator high TA = 25 C frequency and system clock current in stop mode
A
s
%
FIRCTRIM CC C Fast internal RC oscillator trimming step FIRCVAR CC C Fast internal RC oscillator variation in temperature and supply with respect to fFIRC at TA = 55 C in high-frequency configuration
TA = 25 C --
-- -5
1.6 -- +5
% %
1
VDD = 3.3 V 10% / 5.0 V 10%, TA = -40 to 125 C, unless otherwise specified.
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4 40 Freescale Semiconductor
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Electrical characteristics
2 3
All values need to be confirmed during device validation. This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is ON.
4.17
Slow internal RC oscillator (128 kHz) electrical characteristics
Table 37. Slow internal RC oscillator (128 kHz) electrical characteristics
Symbol fSIRC ISIRC3, TSIRCSU SIRCPRE C Parameter Conditions TA = 25 C, trimmed -- TA = 25 C, trimmed
1
The device provides a 128 kHz slow internal RC oscillator. This can be used as the reference clock for the RTC module.
Value2 Unit Min Typ 128 -- -- 8 -- 2.7 -- Max -- 150 5 12 +2 -- +10 % A s % kHz -- 100 -- -- -2
CC P Slow internal RC oscillator low frequency SR -- CC C Slow internal RC oscillator low frequency current
CC P Slow internal RC oscillator start-up TA = 25 C, VDD = 5.0 V 10% time CC C Slow internal RC oscillator precision TA = 25 C after software trimming of fSIRC CC C Slow internal RC oscillator trimming step --
SIRCTRIM SIRCVAR
-- -10
CC C Slow internal RC oscillator variation High frequency configuration in temperature and supply with respect to fSIRC at TA = 55 C in high frequency configuration
VDD = 3.3 V 10% / 5.0 V 10%, TA = -40 to 125 C, unless otherwise specified. All values need to be confirmed during device validation. 3 This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is ON.
1 2
MPC5604B/C Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 41
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Electrical characteristics
4.18
4.18.1
On-chip peripherals
Current consumption
Table 38. On-chip peripherals current consumption1
Value Symbol C Parameter Conditions Min Typ Max A Total (static + dynamic) 7.652 * fperiph + 84.73 consumption: 8.0743 * fperiph + 26.757 * FlexCAN in loop-back mode * XTAL@8MHz used as CAN engine clock source * Message sending period is 580 s 28.7 * fperiph Unit
IDD_BV(CAN)
CC T CAN (FlexCAN) supply 500 Kbps current on VDD_BV 125 Kbps
IDD_BV(eMIOS)
CC T eMIOS supply current on VDD_BV
Static consumption: * eMIOS channel OFF * Global prescaler enabled Dynamic consumption: * It does not change varying the frequency (0.003 mA)
3
IDD_BV(SCI)
CC T SCI (LINFlex) supply current on VDD_BV CC T SPI (DSPI) supply current on VDD_BV
Total (static + dynamic) consumption: * LIN mode * Baudrate: 20 Kbps Ballast static consumption (only clocked) Ballast dynamic consumption (continuus communication): * Baudrate: 2 Mbit * Trasmission every 8 s * Frame: 16 bits
4.7804 * fperiph + 30.946
IDD_BV(SPI)
1 16.3 * fperiph
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4 42 Freescale Semiconductor
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Electrical characteristics
Table 38. On-chip peripherals current consumption1 (continued)
Value Symbol IDD_BV(ADC) C Parameter Conditions Min CC T ADC supply current on VDD = 5.5 V Ballast static consumption VDD_BV (no conversion) VDD = 5.5 V Ballast dynamic consumption (continuus conversion) Typ Max mA 0.0409 * fperiph 0.0049 * fperiph Unit
IDD_HV_ADC(ADC) CC T ADC supply current on VDD = 5.5 V Analog static consumption VDD_HV_ADC (no conversion) VDD = 5.5 V Analog dynamic consumption (continuus conversion) -
0.0017 * fperiph 0.075 * fperiph + 0.032
IDD_HV(FLASH)
CC T CFlash + DFlash supply current on VDD_HV_ADC
VDD = 5.5 V
8.21 (4.14 + 4.07)
IDD_HV(PLL)
1
CC T PLL supply current on VDD = 5.5 V VDD_HV
-
0.0031 * fperiph
Operating conditions: TA = 25 C, fperiph = 8 MHz to 64 MHz
MPC5604B/C Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 43
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Electrical characteristics
4.18.2
DSPI characteristics
Table 39. DSPI characteristics
Value
No. 1 -- -- 2
Symbol tSCK fDSPI
C
Parameter Min Typ -- -- -- Max -- fCPU 1201 64 -- --
Unit ns MHz ns ns
SR D SCK cycle time SR D DSPI digital controller frequency
tCSC CC D Internal delay between pad associated to SCK and pad associated to CSn in master mode tCSCext2 CC D CS to SCK delay SR D
3
Master mode Slave mode Master mode Slave mode Master mode Slave mode -- -- Master (MTFE = 0) Slave Master (MTFE = 1)
tCSCext = tCSC + tCSC 32 -- -- tASCext = tASC + tCSC 1/fDSPI + 5 ns -- tSCK/2 27 0 35 5 35 0 24 0 -- -- -- 2 5.5 2 -- tSCK/2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 32 34 32 -- -- --
3
tASCext CC D After SCK delay SR D
ns ns ns
4
tSDC
CC D SCK duty cycle SR D
5 6 7
tA tDI tSUI
SR D Slave access time SR D Slave SOUT disable time SR D Data setup time for inputs
ns ns ns
8
tHI
SR D Data hold time for inputs
Master (MTFE = 0) Slave Master (MTFE = 1)
ns
9
tSUO5
CC D Data valid after SCK edge
Master (MTFE = 0) Slave Master (MTFE = 1)
ns
10
tHO
(5)
CC D Data hold time for outputs
Master (MTFE = 0) Slave Master (MTFE = 1)
ns
1 2
Maximum is reached when CSn pad is configured as SLOW pad while SCK pad is configured as MEDIUM pad. The tCSC delay value is configurable through a register. When configuring tCSC (using PCSSCK and CSSCK fields in DSPI_CTARx registers), delay between internal CS and internal SCK must be higher than tCSC to ensure positive tCSCext. 3 The t ASC delay value is configurable through a register. When configuring tASC (using PASC and ASC fields in DSPI_CTARx registers), delay between internal CS and internal SCK must be higher than tASC to ensure positive tASCext. 4 This delay value corresponds to SMPL_PT = 00b which is bit field 9 and 8 of DSPI_MCR register. 5 SCK and SOUT configured as MEDIUM pad
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4 44 Freescale Semiconductor
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Electrical characteristics
Figure 15. DSPI classic SPI timing - master, CPHA = 0
2 PCSx 4 SCK Output (CPOL = 0) 4 1
3
SCK Output (CPOL = 1) 9 SIN 10 Data 12 SOUT First Data Data Last Data 11 Last Data
First Data
Note: Numbers shown reference Table 39.
Figure 16. DSPI classic SPI timing - master, CPHA = 1
PCSx
SCK Output (CPOL = 0) 10 SCK Output (CPOL = 1) 9 SIN First Data 12 SOUT First Data Data Data Last Data 11 Last Data
Note: Numbers shown reference Table 39.
MPC5604B/C Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 45
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Electrical characteristics
Figure 17. DSPI classic SPI timing - slave, CPHA = 0
3
2 SS 1 SCK Input (CPOL = 0) 4 SCK Input (CPOL = 1) 5 SOUT First Data 9 SIN 10 Data 12 Data 11 4
6
Last Data
First Data
Last Data
Note: Numbers shown reference Table 39.
Figure 18. DSPI classic SPI timing - slave, CPHA = 1
SS
SCK Input (CPOL = 0)
SCK Input (CPOL = 1) 5 SOUT
11 12 First Data 9 10 Data Last Data Data Last Data 6
SIN
First Data
Note: Numbers shown reference Table 39.
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4 46 Freescale Semiconductor
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Electrical characteristics
Figure 19. DSPI modified transfer format timing - master, CPHA = 0
3 PCSx 4 2 SCK Output (CPOL = 0) SCK Output (CPOL = 1) 9 SIN First Data 12 SOUT First Data Data Data 11 Last Data Last Data 4 1
10
Note: Numbers shown reference Table 39.
Figure 20. DSPI modified transfer format timing - master, CPHA = 1
PCSx
SCK Output (CPOL = 0)
SCK Output (CPOL = 1) 9 SIN First Data Data 12 SOUT First Data Data 10
Last Data 11 Last Data
Note: Numbers shown reference Table 39.
MPC5604B/C Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 47
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Electrical characteristics
Figure 21. DSPI modified transfer format timing - slave, CPHA = 0
3
SS
2 1
SCK Input (CPOL = 0) 4 SCK Input (CPOL = 1) 5 SOUT First Data 9 SIN First Data Data Data 11 12 Last Data 10 Last Data 6 4
Note: Numbers shown reference Table 39.
Figure 22. DSPI modified transfer format timing - slave, CPHA = 1
SS
SCK Input (CPOL = 0)
SCK Input (CPOL = 1) 5 SOUT
11 12 First Data 9 10 Data Last Data Data Last Data 6
SIN
First Data
Note: Numbers shown reference Table 39.
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4 48 Freescale Semiconductor
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Freescale Semiconductor PCSS PCSx
Figure 23. DSPI PCS strobe (PCSS) timing
7
MPC5604B/C Microcontroller Data Sheet, Rev. 4
8
Note: Numbers shown reference Table 39.
Electrical characteristics
49
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Electrical characteristics
4.18.3
Nexus characteristics
Table 40. Nexus characteristics
Value
No. 1 2 3 4 5 10
Symbol tTCYC tMCYC tMDOV tMSEOV tEVTOV tNTDIS tNTMSS
C
Parameter Min Typ -- -- -- -- -- -- -- -- -- -- -- Max -- -- 8 8 8 -- -- -- -- -- -- 64 32 -- -- -- 15 15 5 5 35 6
Unit ns ns ns ns ns ns ns ns ns ns ns
CC D TCK cycle time CC D MCKO cycle time CC D MCKO low to MDO data valid CC D MCKO low to MSEO_b data valid CC D MCKO low to EVTO data valid CC D TDI data setup time CC D TMS data setup time CC D TDI data hold time CC D TMS data hold time CC D TCK low to TDO data valid CC D TCK low to TDO data invalid
11
tNTDIH tNTMSH
12 13
tTDOV tTDOI
Figure 24. Nexus TDI, TMS, TDO timing
TCK
10 11
TMS, TDI
12
TDO
Note: Numbers shown reference Table 40.
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Electrical characteristics
4.18.4
JTAG characteristics
Table 41. JTAG characteristics
Value
No. 1 2 3 4 5 6 7
Symbol tJCYC tTDIS tTDIH tTMSS tTMSH tTDOV tTDOI CC CC CC CC CC CC CC
C
Parameter Min Typ -- -- -- -- -- -- 6 -- Max -- -- -- -- -- 33 -- 64 15 5 15 5
Unit ns ns ns ns ns ns ns
D TCK cycle time D TDI setup time D TDI hold time D TMS setup time D TMS hold time D TCK low to TDO valid D TCK low to TDO invalid
Figure 25. Timing diagram - JTAG boundary scan
TCK
2/4
3/5
DATA INPUTS 6
INPUT DATA VALID
DATA OUTPUTS
OUTPUT DATA VALID
7
DATA OUTPUTS
Note: Numbers shown reference Table 41.
MPC5604B/C Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 51
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Electrical characteristics
4.18.5
4.18.5.1
ADC electrical characteristics
Introduction
Figure 26. ADC characteristic and error definitions
Offset Error OSE 1023 Gain Error GE
The device provides a 10-bit Successive Approximation Register (SAR) analog-to-digital converter.
1022 1021
1020 1019 1 LSB ideal = VDD_ADC / 1024 1018 (2)
code out 7 (1) 6 5 (5) 4 (4) 3 (3) (1) Example of an actual transfer curve (2) The ideal transfer curve (3) Differential non-linearity error (DNL) (4) Integral non-linearity error (INL) (5) Center of a step of the actual transfer curve
2 1
1 LSB (ideal)
0 1 2 3 4 5 6 7 1017 1018 1019 1020 1021 1022 1023 Vin(A) (LSBideal)
Offset Error OSE
4.18.5.2
Input impedance and ADC accuracy
In the following analysis, the input circuit corresponding to the precise channels is considered. To preserve the accuracy of the A/D converter, it is necessary that analog input pins have low AC impedance. Placing a capacitor with good high frequency characteristics at the input pin of the device can be effective: the capacitor should be as large as possible, ideally infinite. This capacitor contributes to attenuating the noise present on the input pin; furthermore, it sources charge during the sampling phase, when the analog signal source is a high-impedance source.
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Electrical characteristics
A real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC filter). The RC filtering may be limited according to the value of source impedance of the transducer or circuit supplying the analog signal to be measured. The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal (bandwidth) and the equivalent input impedance of the ADC itself. In fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: CS being substantially a switched capacitance, with a frequency equal to the conversion rate of the ADC, it can be seen as a resistive path to ground. For instance, assuming a conversion rate of 1 MHz, with CS equal to 3 pF, a resistance of 330 k is obtained (REQ = 1 / (fc*CS), where fc represents the conversion rate at the considered channel). To minimize the error induced by the voltage partitioning between this resistance (sampled voltage on CS) and the sum of RS + RF + RL + RSW + RAD, the external circuit must be designed to respect the Equation 4: Eqn. 4 R S + R F + R L + R SW + R AD -1 V A * -------------------------------------------------------------------------- < -- LSB R EQ 2
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Electrical characteristics
Equation 4 generates a constraint for external network design, in particular on a resistive path. Internal switch resistances (RSW and RAD) can be neglected with respect to external resistances. Figure 27. Input equivalent circuit (precise channels)
EXTERNAL CIRCUIT
INTERNAL CIRCUIT SCHEME VDD Channel Selection RSW1
Sampling
Source RS
Filter RF
Current Limiter RL
RAD
VA
CF
CP1
CP2
CS
RS Source Impedance RF Filter Resistance CF Filter Capacitance RL Current Limiter Resistance RSW1 Channel Selection Switch Impedance RAD Sampling Switch Impedance CP Pin Capacitance (two contributions, CP1 and CP2) CS Sampling Capacitance
Figure 28. Input equivalent circuit (extended channels)
EXTERNAL CIRCUIT
INTERNAL CIRCUIT SCHEME VDD Channel Selection RSW1 Extended Switch RSW2
Sampling
Source RS
Filter RF
Current Limiter RL
RAD
VA
CF
CP1
CP3
CP2
CS
RS RF CF RL RSW RAD CP CS
Source Impedance Filter Resistance Filter Capacitance Current Limiter Resistance Channel Selection Switch Impedance (two contributions RSW1 and RSW2) Sampling Switch Impedance Pin Capacitance (three contributions, CP1, CP2 and CP3) Sampling Capacitance
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Electrical characteristics
A second aspect involving the capacitance network shall be considered. Assuming the three capacitances CF, CP1 and CP2 are initially charged at the source voltage VA (refer to the equivalent circuit in Figure 27): A charge sharing phenomenon is installed when the sampling phase is started (A/D switch close). Figure 29. Transient behavior during sampling phase
VCS VA VA2
Voltage transient on CS V < 0.5 LSB
1 2
1 < (RSW + RAD) CS << TS
VA1
2 = RL (CS + CP1 + CP2)
TS t
In particular two different transient periods can be distinguished: 1. A first and quick charge transfer from the internal capacitance CP1 and CP2 to the sampling capacitance CS occurs (CS is supposed initially completely discharged): considering a worst case (since the time constant in reality would be faster) in which CP2 is reported in parallel to CP1 (call CP = CP1 + CP2), the two capacitances CP and CS are in series, and the time constant is CP * CS 1 = ( R SW + R AD ) * -------------------CP + CS Eqn. 5
Equation 5 can again be simplified considering only CS as an additional worst condition. In reality, the transient is faster, but the A/D converter circuitry has been designed to be robust also in the very worst case: the sampling time TS is always much longer than the internal time constant: Eqn. 6 1 < ( R SW + R AD ) * C S T S The charge of CP1 and CP2 is redistributed also on CS, determining a new value of the voltage VA1 on the capacitance according to Equation 7: Eqn. 7 V A1 * ( C S + C P1 + C P2 ) = V A * ( C P1 + C P2 ) 2. A second charge transfer involves also CF (that is typically bigger than the on-chip capacitance) through the resistance RL: again considering the worst case in which CP2 and CS were in parallel to CP1 (since the time constant in reality would be faster), the time constant is:
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Electrical characteristics
Eqn. 8 2 < R L * ( C S + C P1 + C P2 ) In this case, the time constant depends on the external circuit: in particular imposing that the transient is completed well before the end of sampling time TS, a constraints on RL sizing is obtained: Eqn. 9 10 * 2 = 10 * R L * ( C S + C P1 + C P2 ) < TS Of course, RL shall be sized also according to the current limitation constraints, in combination with RS (source impedance) and RF (filter resistance). Being CF definitively bigger than CP1, CP2 and CS, then the final voltage VA2 (at the end of the charge transfer transient) will be much higher than VA1. Equation 10 must be respected (charge balance assuming now CS already charged at VA1): Eqn. 10 VA2 * ( C S + C P1 + C P2 + C F ) = V A * C F + V A1 * ( C P1 + C P2 + C S ) The two transients above are not influenced by the voltage source that, due to the presence of the RFCF filter, is not able to provide the extra charge to compensate the voltage drop on CS with respect to the ideal source VA; the time constant RFCF of the filter is very high with respect to the sampling time (TS). The filter is typically designed to act as anti-aliasing. Figure 30. Spectral representation of input signal
Analog source bandwidth (VA) Noise TC < 2 RFCF (conversion rate vs. filter pole) fF = f0 (anti-aliasing filtering condition) 2 f0 < fC (Nyquist)
f0
f Sampled signal spectrum (fC = conversion rate)
Anti-aliasing filter (fF = RC filter pole)
fF
f
f0
fC
f
Calling f0 the bandwidth of the source signal (and as a consequence the cut-off frequency of the anti-aliasing filter, fF), according to the Nyquist theorem the conversion rate fC must be at least 2f0; it means that the constant time of the filter is greater than or at least equal to twice the conversion period (TC). Again the conversion period TC is longer than the sampling time TS, which is just a portion of it, even when fixed channel continuous conversion mode is selected (fastest conversion rate at a specific channel): in conclusion it is evident that the time constant of the filter RFCF is definitively much higher than the sampling time TS, so the charge level on CS cannot be modified by the analog signal source during the time in which the sampling switch is closed. The considerations above lead to impose new constraints on the external circuit, to reduce the accuracy error due to the voltage drop on CS; from the two charge balance equations above, it is simple to derive Equation 11 between the ideal and real sampled voltage on CS:
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Electrical characteristics
Eqn. 11 VA C P1 + C P2 + C F ----------- = ------------------------------------------------------V A2 C P1 + C P2 + C F + C S From this formula, in the worst case (when VA is maximum, that is for instance 5 V), assuming to accept a maximum error of half a count, a constraint is evident on CF value: Eqn. 12 C F > 2048 * C S
4.18.5.3
ADC electrical characteristics
Table 42. ADC input leakage current
Value
Symbol C
Parameter
Conditions Min Typ 1 1 8 45 Max -- -- 200 400 -- -- -- --
Unit nA
ILKG CC C Input leakage current TA = -40 C No current injection on adjacent pin C C P TA = 25 C TA = 105 C TA = 125 C
Table 43. ADC conversion characteristics
Symbol VSS_ADC S R C Parameter Conditions1 Min -- Voltage on VSS_HV_ADC (ADC reference) pin with respect to ground (VSS)2 -- Voltage on VDD_HV_ADC pin (ADC reference) with respect to ground (VSS) -- Analog input voltage3 -- ADC analog frequency -- -0.1 Value Typ -- Max 0.1 Uni t V
VDD_ADC S R
--
VDD-0.1
--
VDD+0.1
V
VAINx fADC
S R S R
-- --
VSS_ADC-0.1 6 45 --
-- -- -- --
VDD_ADC+0. 1 32 + 4% 55 1.5
V MH z % s
ADC_SY S R S tADC_PU S R
-- ADC digital clock duty ADCLKSEL = 14 cycle (ipg_clk) -- ADC power up delay --
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Electrical characteristics
Table 43. ADC conversion characteristics (continued)
Symbol tADC_S C C C T Parameter Sample time5 Conditions1 Min fADC = 32 MHz, ADC_conf_sample_input = 17 fADC = 6 MHz, INPSAMP = 255 tADC_C CS CP1 CP2 CP3 RSW1 RSW2 RAD IINJ C C C C C C C C C C C C C C C C S R P Conversion time6 fADC = 32 MHz, ADC_conf_comp = 2 -- -- -- -- -- -- -- VDD = 3.3 V 10% VDD = 5.0 V 10% 0.625 -- -- -- -- -- -- -- -5 -5 0.5 Value Typ -- -- -- -- -- -- -- -- -- -- -- -- 3 3 1 1 3 2 0.1 5 5 42 s pF pF pF pF k k k mA Max Uni t s
D ADC input sampling capacitance D ADC input pin capacitance 1 D ADC input pin capacitance 2 D ADC input pin capacitance 3 D Internal resistance of analog source D Internal resistance of analog source D Internal resistance of analog source
-- Input current Injection Current injection on one ADC input, different from the converted one T T T T P T Absolute value for integral non-linearity Absolute differential non-linearity Absolute offset error Absolute gain error Total unadjusted error7 for precise channels, input only pins Total unadjusted error(7) for extended channel No overload No overload
| INL | | DNL | | OFS | | GNE | TUEp
C C C C C C C C C C
-- -- -- -- -- -- -2 -3 -3 -4
0.5 0.5 0.5 0.6 0.6
1.5 1.0 -- -- 2 3
LSB LSB LSB LSB LSB
Without current injection With current injection
TUEx
C C
T T
Without current injection With current injection
1
3 4
LSB
1
VDD = 3.3 V 10% / 5.0 V 10%, TA = -40 to 125 C, unless otherwise specified.
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Electrical characteristics
2 3 4 5
6 7
Analog and digital VSS must be common (to be tied together externally). VAINx may exceed VSS_ADC and VDD_ADC limits, remaining on absolute maximum ratings, but the results of the conversion will be clamped respectively to 0x000 or 0x3FF. Duty cycle is ensured by using system clock without prescaling. When ADCLKSEL = 0, the duty cycle is ensured by internal divider by 2. During the sample time the input capacitance CS can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tADC_S. After the end of the sample time tADC_S, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tADC_S depend on programming. This parameter does not include the sample time tADC_S, but only the time for determining the digital result and the time to load the result's register with the conversion result. Total Unadjusted Error: The maximum error that occurs without adjusting Offset and Gain errors. This error is a combination of Offset, Gain and Integral Linearity errors.
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60
5 Package characteristics
5.1 Package mechanical data
Figure 31. 144 LQFP package mechanical drawing
Package characteristics
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
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Freescale Semiconductor Package characteristics
MPC5604B/C Microcontroller Data Sheet, Rev. 4
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Package characteristics
Figure 32. 100 LQFP package mechanical drawing
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
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Freescale Semiconductor Package characteristics
MPC5604B/C Microcontroller Data Sheet, Rev. 4
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64
Package characteristics
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4
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Freescale Semiconductor
Figure 33. 208 MAPBGA package mechanical drawing
MPC5604B/C Microcontroller Data Sheet, Rev. 4
Package characteristics
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Package characteristics
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Ordering information
6
Ordering information
Table 44. Orderable Part Number Summary
Orderable Part Number MPC5602BEMLL MPC5602BEMLLR MPC5602BEMLQ MPC5602BEMLQR MPC5602CEMLL MPC5602CEMLLR MPC5603BEMLL MPC5603BEMLLR MPC5603BEMLQ MPC5603BEMLQR MPC5603CEMLL MPC5603CEMLLR MPC5602BEVLL MPC5602BEVLLR MPC5602BEVLQ MPC5602BEVLQR MPC5602CEVLL MPC5602CEVLLR MPC5603BEVLL MPC5603BEVLLR MPC5603BEVLQ MPC5603BEVLQR MPC5603CEVLL MPC5603CEVLLR MPC5604BEMLL MPC5604BEMLLR MPC5604BEMLQ MPC5604BEMLQR MPC5604BEVLL MPC5604BEVLLR e200z0h 512 / 32 100 LQFP -40 to 105 64 4 x 16 KB 3.3/5 V e200z0h 512 / 32 144 LQFP -40 to 125 60 4 x 16 KB 3.3/5 V e200z0h 512 / 32 100 LQFP -40 to 125 60 4 x 16 KB 3.3/5 V e200z0h 384 / 40 100 LQFP -40 to 105 64 4 x 16 KB 3.3/5 V e200z0h 384 / 28 144 LQFP -40 to 105 64 4 x 16 KB 3.3/5 V e200z0h 384 / 28 100 LQFP -40 to 105 64 4 x 16 KB 3.3/5 V e200z0h 256 / 32 100 LQFP -40 to 105 64 4 x 16 KB 3.3/5 V e200z0h 256 / 24 144 LQFP -40 to 105 64 4 x 16 KB 3.3/5 V e200z0h 256 / 24 100 LQFP -40 to 105 64 4 x 16 KB 3.3/5 V e200z0h 384 / 40 100 LQFP -40 to 125 60 4 x 16 KB 3.3/5 V e200z0h 384 / 28 144 LQFP -40 to 125 60 4 x 16 KB 3.3/5 V e200z0h 384 / 28 100 LQFP -40 to 125 60 4 x 16 KB 3.3/5 V e200z0h 256 / 32 100 LQFP -40 to 125 60 4 x 16 KB 3.3/5 V e200z0h 256 / 24 144 LQFP -40 to 125 60 4 x 16 KB 3.3/5 V CPU e200z0h Code Flash / SRAM (Kbytes) 256 / 24 Package Operating Speed temp. (MHz) (C) 60 Data Flash Voltage Packing Tray Tape & Reel Tray Tape & Reel Tray Tape & Reel Tray Tape & Reel Tray Tape & Reel Tray Tape & Reel Tray Tape & Reel Tray Tape & Reel Tray Tape & Reel Tray Tape & Reel Tray Tape & Reel Tray Tape & Reel Tray Tape & Reel Tray Tape & Reel Tray Tape & Reel
100 LQFP -40 to 125
4 x 16 KB 3.3/5 V
MPC5604B/C Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 67
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Document revision history
Table 44. Orderable Part Number Summary (continued)
Orderable Part Number MPC5604BEVLQ MPC5604BEVLQR MPC5604CEMLL MPC5604CEMLLR MPC5604BEMMG
1
CPU e200z0h
Code Flash / SRAM (Kbytes) 512 / 32
Package
Operating Speed temp. (MHz) (C) 64
Data Flash
Voltage
Packing Tray Tape & Reel
144 LQFP -40 to 105
4 x 16 KB 3.3/5 V
e200z0h
512 / 48
100 LQFP -40 to 125
60
4 x 16 KB 3.3/5 V
Tray Tape & Reel
e200z0h
512 / 48
208 MAP -40 to 125 BGA1
64
4 x 16 KB 3.3/5 V
Tray
208 MAPBGA available only as development package for Nexus2+
Figure 34. Commercial product code structure
Example code: Qualification Status PowerPC Core Automotive Platform Core Version Flash Size (core dependent) Product Optional fields Temperature spec. Package Code R = Tape & Reel (blank if Tray) M PC 56 0 4 B E M LL R
Qualification Status
M = MC status S = Auto qualified P = PC status
Flash Size (z0 core)
2 = 256 KB 3 = 384 KB 4 = 512 KB
Temperature spec.
C = -40 to 85 C V = -40 to 105 C M = -40 to 125 C
Automotive Platform
56 = PPC in 90nm 57 = PPC in 65nm
Product
B = Body C = Gateway
Package Code
LL = 100 LQFP LQ = 144 LQFP MG = 208 MAPBGA1
1
208 MAPBGA available only as development package for Nexus2+
7
Document revision history
Table 45. Revision history
Revision 1 Date 04-Apr-2008 Initial release. Description of Changes
Table 45 summarizes revisions to this document.
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Document revision history
Table 45. Revision history (continued)
Revision 2 Date Description of Changes
06-Mar-2009 Made minor editing and formatting changes to improve readability Harmonized oscillator naming throughout document Features: --Replaced 32 KB with 48 KB as max SRAM size --Updated descripiton of INTC --Changed max number of GPIO pins from 121 to 123 Updated Section 1.1, "Introduction Updated Table 2 Added Section 2, "Device blocks Section 3, "Package pinouts: Removed signal descriptions (these are found in the device reference manual) Updated Figure 2: --Replaced VPP with VSS_HV on pin 18 --Added MA[1] as AF3 for PC[10] (pin 28) --Added MA[0] as AF2 for PC[3] (pin 116) --Changed description for pin 120 to PH[10] / GPIO[122] / TMS --Changed description for pin 127 to PH[9] / GPIO[121] / TCK --Replaced NMI[0] with NMI on pin 11 Updated Figure 3: --Replaced VPP with VSS_HV on pin 14 --Added MA[1] as AF3 for PC[10] (pin 22) --Added MA[0] as AF2 for PC[3] (pin 77) --Changed description for pin 81 to PH[10] / GPIO[122] / TMS --Changed description for pin 88 to PH[9] / GPIO[121] / TCK --Removed E1UC[19] from pin 76 --Replaced [11] with WKUP[11] for PB[3] (pin 1) --Replaced NMI[0] with NMI on pin 7 Updated Figure 4: --Changed description for ball B8 from TCK to PH[9] --Changed description for ball B9 from TMS to PH[10] --Updated descriptions for balls R9 and T9 Added Section 3.2, "Parameter classification and tagged parameters in tables where appropriate Added Section 3.3, "NVUSRO register Updated Table 7 Section 3.5, "Recommended operating conditions: Added note on RAM data retention to end of section Updated Table 8 and Table 9 Added Section 3.6.1, "Package thermal characteristics Updated Section 3.6.2, "Power considerations Updated Figure 6 Updated Table 12, Table 13, Table 14, Table 15 and Table 16
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Document revision history
Table 45. Revision history (continued)
Revision 2 Date Description of Changes
06-Mar-2009 Added Section 3.7.4, "Output pin transition times Updated Table 19 Updated Figure 7 Updated Table 20 Section 3.9.1, "Voltage regulator electrical characteristics: Amended description of LV_PLL Figure 9: Exchanged position of symbols CDEC1 and CDEC2 Updated Table 21 Added Figure 10 Updated Table 22 and Table 23 Updated Section 3.11, "Flash memory electrical characteristics Added Section 3.12, "Electromagnetic compatibility (EMC) characteristics Updated Section 3.13, "Fast external crystal oscillator (4 to 16 MHz) electrical characteristics Updated Section 3.14, "Slow external crystal oscillator (32 kHz) electrical characteristics Updated Table 37, Table 38 and Table 39 Added Section 3.18, "On-chip peripherals Added Table 44 Updated Table 45 Updated Table 49 Added Section Appendix A, "Abbreviations 06-Aug-2009 Updated Figure 4 Table 7 * VDD_ADC: changed min value for "relative to VDD" condition * VIN: changed min value for "relative to VDD" condition * ICORELV: added new row Table 9 * TA C-Grade Part, TJ C-Grade Part, TA V-Grade Part, TJ V-Grade Part, TA M-Grade Part, TJ M-Grade Part: added new rows * Changed capacitance value in footnote Table 17 * MEDIUM configuration: added condition for PAD3V5V = 0 Updated Figure 9 Table 21 * CDEC1: changed min value * IMREG: changed max value * IDD_BV: added max value footnote Table 22 * VLVDHV3H: changed max value * VLVDHV3L: added max value * VLVDHV5H: changed max value * VLVDHV5L: added max value Updated Table 23 Table 26 * Retention: deleted min value footnote for "Blocks with 100,000 P/E cycles" Table 34 * IFXOSC: added typ value Table 36 * VSXOSC: changed typ value * TSXOSCSU: added max value footnote Table 37 * tLTJIT: added max value Updated Figure 33
4
MPC5604B/C Microcontroller Data Sheet Data Sheet, Rev. 4 70 Freescale Semiconductor
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Abbreviations Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5604BxMG products in 208 MAPBGA packages 71
Appendix A Abbreviations
Table 46 lists abbreviations used but not defined elsewhere in this document. Table 46. Abbreviations
Abbreviation CMOS CPHA CPOL CS EVTO LED MCKO MDO MSEO MTFE SCK SOUT TBD TCK TDI TDO TMS Meaning Complementary metal-oxide-semiconductor Clock phase Clock polarity Peripheral chip select Event out Light emitting diode Message clock out Message data out Message start/end out Modified timing format enable Serial communications clock Serial data out To be defined Test clock input Test data input Test data output Test mode select
MPC5604B/C Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor
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